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Elulookirjeldus (CV)
1.Eesnimi Jaan
2.Perekonnanimi Raik
3.Töökoht Tallinna Tehnikaülikooli Arvutitehnika instituut
4.Ametikoht vanemteadur
5.Sünniaeg 09.01.1972 (päev.kuu.aasta)
6.Haridus 2001 tehnikateaduste doktor, TTÜ
1997 tehnikateaduste magister, TTÜ
1995 astusin TTÜ magistriõppesse
1990 astusin TTÜ Automaatika teaduskonda
1990 lõpetasin Tallinna 44. Keskkooli
7.Teenistuskäik 2002- vanemteadur, TTÜ
1998-2002 teadur, TTÜ
1995-1998 assistent, TTÜ
Pikemad visiidid välisinstituutidesse:
2005 Fraunhoferi Instituut, Dresden, Saksa, teadur, 20 päeva
2000-2002 Stuttgarti Ülikool, Saksamaa, teadur, 3 kuud
1997-99 Fraunhoferi Instituut, Dresden, Saksa, teadur, 6 kuud
1996 Michigan State University, USA, vahetusüliõpilane, 1,5 kuud
1995 Grenoble'i Rahvuslik Polütehniline Instituut, teadur, 1,5 kuud
1994 Grenoble'i Rahvuslik Polütehniline Instituut, tudeng, 2 kuud
1994 Darmstadti Tehnikaülikool, Saksamaa, tudeng, 3 kuud
8.Teaduskraad tehnikateaduste doktor
9.Teaduskraadi välja
andnud asutus, aasta		 Tallinna Tehnikaülikool, 2001
10.Tunnustused 2004 Vabariigi presidendi Kultuurirahastu "Noore teadlase preemia"
2004 Akadeemik Boris Tamme nim. stipendium
2001 Gebert-Rüf'i Fondi stipendium (Shveitsi teaduspreemia)
2000 TTÜ Arengufondi stipendium
1999 I preemia Haridusministeeriumi üliõpilastööde teaduskonkursil
1998 III preemia Haridusministeeriumi üliõpilastööde teaduskonkursil
1997 'Mente et manu' medal teaduskonna parimale lõpetajale
1997 I preemia Haridusministeeriumi üliõpilastööde teaduskonkursil
1996 III preemia ajakirja "Baltic Electronics" ja Motorola Balti riikide üliõpilastööde teaduskonkursil
1994 I preemia Haridus- ja kultuuriministeeriumi üliõpilastööde teaduskonkursil
11.Teadusorganisatsiooniline
ja –administratiivne
tegevus		 European Test Symposium 2005 kohaliku koraldusgrupi juht (Chair),
konverentside ACM/IEEE Design Automation and Test in Europe, IEEE European Test Symposium, European Dependable Computing Conference ja East-West Design and Test Workshop programmikomiteede liige,
IEEE Computer Society ja Test Technology Technical Council liige, Nordic Test Forumi liige.
12.Juhendamisel kaitstud
väitekirjad

Anna Krivenko, MSc, 2005, juh. Jaan Raik. Experimental Analysis of Hierarchical Test Generator DECIDER. Tallinna Tehnikaülikool

Joachim Sudbrock, MSc, 2005, juh. Jaan Raik, Raimund Ubar, Thomas Hollstein. Defect Oriented Automated Test Pattern Generation for Standard Cell ASIC Designs. TU Darmstadt

Vineeth Govind, MSc, 2004, juh. Jaan Raik, Raimund Ubar, Hannu Tenhunen. RT-level test point insertion for improving testability in sequential circuits. KTH, Stockholm

Rein Raidma, MSc, 2003, juh. Jaan Raik, Raimund Ubar. Kontrollitavuse parandamisel põhinev järjestikskeemide isetesti meetod. Tallinna Tehnikaülikool

Margit Aarna, MSc, 2001, juh. Jaan Raik. Digitaalskeemide rikete paralleelnesimuleerimine binaarsetel otsustusdiagrammidel. Tallinna Tehnikaülikool
13.Teadustöö põhisuunad Kõrgtaseme testigenereerimine, dünaamiline verifitseerimine, testide hulga minimiseerimine, diagnostika akseleraatorid, defekt-orienteeritud test, süsteemide modelleerimine otsustusdiagrammide abil.
120 publikatsiooni rahvusvaheliselt retsenseeritavates teaduslikes väljaannetes.
14.Jooksvad grandid 5637, Kõrgtaseme testigenereerimine ja testitavuse analüüs digitaalskeemidele, 2003-2005, J. Raik
5910, Isetestivad digitaalsüsteemid, 2004-2007, R. Ubar
15.Teaduspublikatsioonid

A.Jutman, J.Raik, R.Ubar. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419.

A. Jutman, J. Raik, R. Ubar. New Built-In Self-Test Scheme for SoC interconnect. 9th World Multiconference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, USA, 2005

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. Proc. of the EUROMICRO Conference on Digital Systems Design, Porto, Portugal, 2005.

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz,W.Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. 6th IEEE Latin-American Test Workshop – LATW2005, pp. 325-330, Salvador de Bahia, Brazil, March 30 - April 2, 2005.

J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Springer Lecture Notes in Computer Science, Proceedings of the 5th European Dependable Computing Conference, Springer, pp. 332-344, 2005.

J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications, Springer Science, Vol. 21, No. 1, pp.71-82, February 2005.

J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

J.Sudbrock, R.Ubar, J.Raik, W.Kuzmicz,W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proceedings of the IEEE European Test Symposium, IEEE Computer Society, Los Alamitos, USA, pp. 96-101, May 22-25, 2005.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Teaching Advanced Test Issues in Digital Electronics. 6th IEEE International Conference on Information Technology Based Higher Education and Training. July 7-9, 2005, Santo Domingo, pp. S2B-5 – S2B-10.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar, J.Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Proceedings of the IEEE European Test Symposium, pp. 151-155, Tallinn, Estonia, May 22-25, 2005.

A.Jutman, A.Peder, J.Raik, M.Tombak, R. Ubar. Structurally synthesized binary decision diagrams. 6th International Workshop on Boolean Problems, pp. 271-278, Freiberg, Germany, Sept. 23-24, 2004.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H.-D. Wuttke. Research Environment for Teaching Digital Test. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 468-473, Ilmenau, Germany, September 27-30, 2004.

E.Ivask, J.Raik, R.Ubar, A.Schneider. Web-Based Environment Using Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, Kluwer Academic Publishers, pp. 435-442, Tolouse, France, Aug. 22-27, 2004.

J. Raik, A. Krivenko, R. Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the Baltic Electronic Conference, pp. 225-228, Tallinn, Estonia, Oct. 3-6, 2004.

J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST with Status Bit Control. 11th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES, pp. 507-510, Szczecin, Poland, June 24-26, 2004.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. Proc. of the East-West Design & Test Workshop - EWDTW'04, pp. 35-40, July-Sept. 2004.

J.Raik, R.Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS, pp.219-222, Stara Lesna, Slovakia, April 18-21, 2004.

J.Raik, R.Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. Digest of papers of the European Test Symposium, pp. 17-18, Ajaccio, France, May 23-26, 2004.

J.Raik, V.Govind, R.Ubar. RTL Test Point Insertion for Sequential Circuits. Proc. of the International Workshop on Testability Assessment (IWoTA), Rennes, France, 2004

P.Ellervee, J.Raik, V. Tihhomirov. Environment for Fault Simulation Acceleration on FPGA. Proc. of the Baltic Electronic Conference, pp. 217-220, Tallinn, Estonia, Oct. 3-6, 2004.

P.Ellervee, J.Raik, V. Tihhomirov, K.Tammemäe. Evaluating Fault Emulation on FPGA. Field-Programmable Logic and Applications. 14th International Conference , FPL 2004. Eds. J.Becker, M.Platzner, S.Vernalde, Springer Verlag, pp. 354-363, Antwerp, Belgium, Aug. 30 – Sept. 1, 2004.

P.Ellervee, J.Raik, V. Tihhomirov, R.Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 2004.

R. Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004, Vol. 2, pp. 459-462, Sinaia, Romania, Oct. 4-6, 2004.

R. Ubar, T. Vassiljeva, J.Raik, A.Jutman, M.Tombak, A.Peder. Optimization of Structurally Synthesized BDDs. Proc of the 4th IASTED International Conference on Modelling, Simuation, and Optimization MSO 2004, pp. 234-240, Kauai, Hawaii, USA, Aug. 17-19, 2004.

V.Vislogubov, A. Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the Baltic Electronic Conference, pp. 255-258, Tallinn, Estonia, Oct. 3-6, 2004.

A.Mekler, J.Raik. Multiple-Objective Backtrace for Solving Test Generation Constraints. Proc. of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 19-21, 2003.

A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. World Multiconference on Systemics, Cybernetics and Informatics. Vol. VIII, pp. 136-141, Orlando, Florida, July 27-30, 2003.

J.Raik, R.Raidma, R.Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. Proc. of the Norchip Conference, Riga, Latvia, Nov. 11-12, 2003.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester - Diagnostic Package for Research and Training. East-West Design & Test Conference - EWDTC'03, Scientific-Technical Journal Radioelectronics and Informatics, No. 3 (24), pp. 69-73, July-Sept. 2003.

P.Ellervee, J.Raik, V.Tihomirov. Fault Emulation on FPGA: A Feasibility Study. Proc. of the Norchip Conference, Nov. 11-12, 2003.

R.Ubar, J.Raik, B.Klüver. Algorithms for hierarchical fault simulation in digital systems. MIXDES Conference, pp. 530-535, Lodz, Poland, June 26-28, 2003.

R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In "Networks on Chip" by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. 23rd Int. Conf. on Microelectronics, Vol.2, pp.621-624, Nis, Yugoslavia, May 12-15 2002.

A.Jutman, J.Raik, R.Ubar. SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation and Test. Proc. of the 5th International Workshop on Boolean Problems. pp. 157-166, Sept. 19-20, 2002, Freiberg, Germany.

A.Schneider, E.Ivask, P.Miklos, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of Design Automation and Test in Europe - DATE02, pp. 221-226, Paris, March 4-8, 2002.

A. Schneider, K.-H. Diener, G. Elst, E. Ivask, J. Raik, R. Ubar. Internet-Based Testability-Driven Test Generation in Virtual Environment MOSCITO, Proc. of the International Workshop on IP-Based SoC Design, Oct. 30-31, 2002, Grenoble, France.

A. Schneider , K.-H. Diener , G. Jervan , Z. Peng , J. Raik ,R. Ubar , T. Hollstein , M. Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.

J. Raik, A. Jutman, R. Ubar. Exact Static Compaction of Independent Test Sequences. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests using branch-and-bound and Search State Registration, IEEE European Test Workshop, Corfu, Greece, May 26-29, 2002.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the ICECS 2002 Conference. Vol. II, pp. 445-448, Sept. 15-18, 2002, Dubrovnik, Croatia.

R.Ubar, A.Jutman, E. Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. Microelectronics Education. Proc. of the 4th European Workshop on Microelectronics Education. Marcombo publishers, pp. 317-320, May 23-24, 2002, University of Vigo, Spain.

R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics, Vol.2, pp.617-620, Nis, Yugoslavia, May 12-15 2002.

R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams, IEEE Workshop on Electronic Design, Test and Applications - DELTA02, pp.86-91, Christchurch, New Zealand, 29-31 January 2002.

R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams, Proc. of the NORCHIP Conference, Nov. 11-12, 2002, Copenhagen, Denmark.

T. Cibakova, M. Fischerova, E. Gramatova, W. Kuzmicz, W.A. Pleskacz, J. Raik, R. Ubar. Hierarchical test generation for combinational circuits with real defects coverage, Journal of Microelectronics Reliability. Pergamon Press. Vol 42/7, pp 1141-1149, July 2002.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search, Digest of European Test Workshop, pp. 207-210, Stockholm, May 29 - June 1, 2001.

M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits, Proc. of 42th International Scientific Conference of Riga Technical University, pp.91-94, Riga, October 11-13, 2001.

M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements, Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, pp 2023-2040, Dec. 2001.

R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems, Proceedings of Int. Symp. on Signals, Circuits and Systems SCS 2001, pp.181-184, Iasi, Romania, July 10-11, 2001.

T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation, Proc. of the Design and Diagnostics of Electronic Circuits and Systems DDECS'2001 Conference, pp. 163-168, Györ, Hungary, April 18-20, 2001.

T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. MIXDES 01, pp.131-136, Zakopane, Poland, June 21-23, 2001.

W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits, 2nd International Symposium on Quality of Electronic Design, pp. 365-371, San Jose, California, USA, 2001

A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

A.Morawiec, R.Ubar, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. Proceedings of the DATE Conference, p. 743, Paris, France, March 27-30, 2000.

E.Ivask, J.Raik, R.Ubar. Fault-Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, pp. 319-320 Cascais, Portugal, May 23-26, 2000.

J.Raik. Greedy Alternative for the Static Compaction of Sequential Circuit Test Sequences. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

J. Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, June, 2000.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. Formal Proceedings of the IEEE European Test Workshop, pp. 69-74, Cascais, Portugal, May 23-26, 2000.

M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams, Proc. of the IEEE ISCAS'2000 Conference, Vol. 1, pp. 208-211, Geneva, Switzerland, May 28-31, 2000.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems, International Symposium on Quality of Electronic Design, pp. 189-195, San Jose, California, USA, March 20-22, 2000.

A.Markus, J.Raik, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representation, Proc. of the Second Electronic Circuits and Systems Conference ECS'99, pp. 17-20, Bratislava, Slovakia, Sept. 6-8, 1999.

G.Jervan, P.Eles, Z.Peng, J.Raik, R.Ubar. High-Level Test Synthesis with Hierarchical Test Generation, Proc. of the NORCHIP Conference, pp. 291-296, Oslo, Norway, Nov. 8-9, 1999.

J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Proc. of the European Test Workshop, pp. 84-89, Konstanz, Germany, May 25-28, 1999.

J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Proc. of the European Test Workshop, pp. 84-89, Konstanz, Germany, May 25-28, 1999.

J.Raik, R.Ubar. Sequential Circuit Test Generation Using Decision Diagram Models, Proceedings of the DATE Conference, pp. 736-740, Munich, Germany, March 9-12, 1999.

K.H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. FPGA Design Flow with Automated Test Generation, Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems, pp. 120-123, Potsdam, Germany, Feb 28-Mar 2, 1999.

R.Ubar, A.Morawiec, J.Raik. Cycle-based Simulation with Decision Diagrams, Proceedings of the DATE Conference, pp. 454-458, Munich, Germany, March 9-12, 1999.

A.Markus, J.Raik, R.Ubar. Test Set Minimization using Bipartite Graphs. Proc. of the BEC'98 Conference, pp. 175-178, Tallinn, Estonia, Oct. 7-9, 1998.

E. Ivask, J.Raik, R.Ubar. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the BEC'98 Conference, pp. 163-166, Tallinn, Estonia, Oct. 7-9, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct. 7-9, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: A Decision Diagram based Hierarchical Test Generation System. Proc. of the DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation with Multi-Level Decision Diagram Models. Proc. of the 7-th IEEE North Atlantic Test Workshop, pp. 26-33, West Greenwich, RI, USA, May 28-29, 1998.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A CAD System for Teaching Digital Test. Microelectronics Education. Proc. of the 2nd European Workshop on Microelectronics Education, Kluwer Academic Publishers, pp. 287-290, Noordwijkerhout, the Netherlands, May 14-15, 1998.

G.Jervan, A.Markus, R.Ubar, J.Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., pp. 335-340, Lodz, Poland, June 18-20, 1998.

G.Jervan, A.Markus, R.Ubar, J.Raik. VHDL based Test Generation System. Proc. of the 5th Int. Conf. on Electronic Devices and Systems, pp. 145-148, Brno, Czech Republic, June 11-12, 1998.

J.Raik, R.Ubar. Feasibility of Structurally Synthesized BDD Models for Test Generation. Compendium of Papers of the European Test Workshop, pp. 145-146, Barcelona, May 27-29, 1998.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998.

R. Ubar, J. Heinlaid, L. Raun, J. Raik. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams. Proc. of the BEC'98 Conference, pp. 179-182, Tallinn, Estonia, Oct. 7-9, 1998.

R. Ubar, J. Raik. Hierarchical test generation for digital systems based on combining bottom-up and top-down approaches. Proc. of the World Multiconference SCI'98 / ISAS'98, pp. 374-381, Orlando, USA, July 12-16, 1998.

A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 212-216, Paris, France, October 20-22, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Assembling Low-Level Tests to High-Level Test Frames. Proc. of the IEEE 15th NORCHIP Conf. pp. 275-280, Tallinn, Estonia, Nov. 10-11, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the International Conference on Design and Diagnostics of Electronic Circuits and Systems '97. pp. 35-40, Beskydy Mountains, Czech Republic, May 12-16, 1997.

M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Mixed-Level Test Generator for Digital Systems. Proc. of the Estonian Acad. of Sci. Engng. Vol. 3, No. 4, pp. 269-280, Tallinn, Estonia, 1997.

R.Ubar, J.Raik. Multi-Valued Simulation With Binary Decision Diagrams. Compedium of Papers of IEEE European Test Workshop. pp. 28-29, Cagliari, Italy, May 28-30, 1997.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996.

J.Raik, P.Paomets. Test Synthesis from Register-Transfer Level Descriptions. Proc. of the 5-th Baltic Electronics Conference. pp. 311-314, Tallinn, Estonia, Oct. 1996.

J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996.

R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996.

R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb. 1996.

R.Ubar, A.Buldas, P.Paomets, J.Raik, V.Tulit. A PC-based CAD System for Training Digital Test. Proc. of the V EUROCHIP Workshop on VLSI Design Training. pp. 152-157, Dresden, Germany, Oct. 1994.

viimati muudetud: 26.09.2005

Curriculum Vitae (CV)
1.First Name Jaan
2.Surname Raik
3.Institution Tallinn University of Technology, Department of Computer Engineering
4.Position senior researcher
5.Date of birth 09.01.1972 (day.month.year)
6.Education 2001 received PhD at TTU
1997 received MSc at TTU
1995 entered Master studies
1990 entered Faculty of Automation of TTU
1990 graduated English-biased Tallinn’s Secondary School No. 44
7.Research and
professional experience		 2002- senior researcher, TTU
1998-2002 researcher, TTU
1995-1998 assistant, TTU
Longer stays at foreign institutes:
2005 Fraunhofer Institute, Dresden, Germany, researcher, 20 days
2000-2002 University of Stuttgart, Germany, researcher, 3 months
1997-1999 Fraunhofer Institute, Dresden, Germany, researcher, 6 months
1996 Michigan State University, USA, exchange student, 1,5 months
1995 National Polytechnical Institute Grenoble, France, researcher, 1,5 months
1994 National Polytechnical Institute Grenoble, student, 2 months
1994 Darmstadt University of Technology, Germany, student, 3 months
8.Academic degree Ph. D.
9.Dates and sites of
earning the degrees		 Tallinn University of Technology, 2001
10.Honours/awards 2004 Estonian Young Scientist Prize by the Cultural Foundation of the President of Estonia
2004 Boris Tamm Scholarship
2001 Swiss Gebert-Rüf Foundation Graduate Science Award
2000 Scholarship of Development Foundation of TTU
1999 I prize at the contest of student works by Estonian Ministry of Education
1998 III prize at the contest of student works by Estonian Ministry of Education
1997 ‘Mente et manu’ medal for the best graduate of the faculty
1997 I prize at the contest of student works by Estonian Ministry of Education
1996 III prize in the contest by Baltic Electronics and Motorola for the students of the Baltic States in the field of electronics and related fields
1994 I prize at the contest of student works by Estonian Ministry of Education and Culture
11.Research-administrative
experience		 Local organization chair of European Test symposium 2005,
Program Committee member of ACM/IEEE Design Automation and Test in Europe, IEEE European Test Symposium, European Dependable Computing Conference and East-West Design&Test Workshop,
Member of IEEE Computer Society, Test Technology Technical Council and Nordic Test Forum
12.Supervised dissertations

Anna Krivenko, MSc, 2005, superv. Jaan Raik. Experimental Analysis of Hierarchical Test Generator DECIDER. Tallinna Tehnikaülikool

Joachim Sudbrock, MSc, 2005, superv. Jaan Raik, Raimund Ubar, Thomas Hollstein. Defect Oriented Automated Test Pattern Generation for Standard Cell ASIC Designs. TU Darmstadt

Vineeth Govind, MSc, 2004, superv. Jaan Raik, Raimund Ubar, Hannu Tenhunen. RT-level test point insertion for improving testability in sequential circuits. KTH, Stockholm

Rein Raidma, MSc, 2003, superv. Jaan Raik, Raimund Ubar. Kontrollitavuse parandamisel põhinev järjestikskeemide isetesti meetod. Tallinna Tehnikaülikool

Margit Aarna, MSc, 2001, superv. Jaan Raik. Digitaalskeemide rikete paralleelnesimuleerimine binaarsetel otsustusdiagrammidel. Tallinna Tehnikaülikool
13.Current research program High-level test generation, dynamic verification, test set compaction, test accelerators, defect-oriented testing, simulating systems represented by decision diagrams.
120 scientific publications at international level
14.Current grant funding 5637,High-Level Test Generation and Testability Analysis for Digital Circuits, 2003-2005, J. Raik
5910, Self-Testing Digital Systems, 2004-2007, R. Ubar
15.List of most important publications

A.Jutman, J.Raik, R.Ubar. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419.

A. Jutman, J. Raik, R. Ubar. New Built-In Self-Test Scheme for SoC interconnect. 9th World Multiconference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, USA, 2005

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. Proc. of the EUROMICRO Conference on Digital Systems Design, Porto, Portugal, 2005.

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz,W.Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. 6th IEEE Latin-American Test Workshop – LATW2005, pp. 325-330, Salvador de Bahia, Brazil, March 30 - April 2, 2005.

J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Springer Lecture Notes in Computer Science, Proceedings of the 5th European Dependable Computing Conference, Springer, pp. 332-344, 2005.

J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications, Springer Science, Vol. 21, No. 1, pp.71-82, February 2005.

J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. 8th IEEE Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

J.Sudbrock, R.Ubar, J.Raik, W.Kuzmicz,W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proceedings of the IEEE European Test Symposium, IEEE Computer Society, Los Alamitos, USA, pp. 96-101, May 22-25, 2005.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Teaching Advanced Test Issues in Digital Electronics. 6th IEEE International Conference on Information Technology Based Higher Education and Training. July 7-9, 2005, Santo Domingo, pp. S2B-5 – S2B-10.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar, J.Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Proceedings of the IEEE European Test Symposium, pp. 151-155, Tallinn, Estonia, May 22-25, 2005.

A.Jutman, A.Peder, J.Raik, M.Tombak, R. Ubar. Structurally synthesized binary decision diagrams. 6th International Workshop on Boolean Problems, pp. 271-278, Freiberg, Germany, Sept. 23-24, 2004.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H.-D. Wuttke. Research Environment for Teaching Digital Test. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 468-473, Ilmenau, Germany, September 27-30, 2004.

E.Ivask, J.Raik, R.Ubar, A.Schneider. Web-Based Environment Using Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks, IFIP 18th World Computer Congress, Kluwer Academic Publishers, pp. 435-442, Tolouse, France, Aug. 22-27, 2004.

J. Raik, A. Krivenko, R. Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the Baltic Electronic Conference, pp. 225-228, Tallinn, Estonia, Oct. 3-6, 2004.

J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST with Status Bit Control. 11th International Conference on Mixed Design of Integrated Circuits and Systems MIXDES, pp. 507-510, Szczecin, Poland, June 24-26, 2004.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. Proc. of the East-West Design & Test Workshop - EWDTW'04, pp. 35-40, July-Sept. 2004.

J.Raik, R.Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS, pp.219-222, Stara Lesna, Slovakia, April 18-21, 2004.

J.Raik, R.Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. Digest of papers of the European Test Symposium, pp. 17-18, Ajaccio, France, May 23-26, 2004.

J.Raik, V.Govind, R.Ubar. RTL Test Point Insertion for Sequential Circuits. Proc. of the International Workshop on Testability Assessment (IWoTA), Rennes, France, 2004

P.Ellervee, J.Raik, V. Tihhomirov. Environment for Fault Simulation Acceleration on FPGA. Proc. of the Baltic Electronic Conference, pp. 217-220, Tallinn, Estonia, Oct. 3-6, 2004.

P.Ellervee, J.Raik, V. Tihhomirov, K.Tammemäe. Evaluating Fault Emulation on FPGA. Field-Programmable Logic and Applications. 14th International Conference , FPL 2004. Eds. J.Becker, M.Platzner, S.Vernalde, Springer Verlag, pp. 354-363, Antwerp, Belgium, Aug. 30 – Sept. 1, 2004.

P.Ellervee, J.Raik, V. Tihhomirov, R.Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 2004.

R. Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004, Vol. 2, pp. 459-462, Sinaia, Romania, Oct. 4-6, 2004.

R. Ubar, T. Vassiljeva, J.Raik, A.Jutman, M.Tombak, A.Peder. Optimization of Structurally Synthesized BDDs. Proc of the 4th IASTED International Conference on Modelling, Simuation, and Optimization MSO 2004, pp. 234-240, Kauai, Hawaii, USA, Aug. 17-19, 2004.

V.Vislogubov, A. Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the Baltic Electronic Conference, pp. 255-258, Tallinn, Estonia, Oct. 3-6, 2004.

A.Mekler, J.Raik. Multiple-Objective Backtrace for Solving Test Generation Constraints. Proc. of the International Symposium on System-on-Chip, Tampere, Finland, Nov. 19-21, 2003.

A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. World Multiconference on Systemics, Cybernetics and Informatics. Vol. VIII, pp. 136-141, Orlando, Florida, July 27-30, 2003.

J.Raik, R.Raidma, R.Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. Proc. of the Norchip Conference, Riga, Latvia, Nov. 11-12, 2003.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester - Diagnostic Package for Research and Training. East-West Design & Test Conference - EWDTC'03, Scientific-Technical Journal Radioelectronics and Informatics, No. 3 (24), pp. 69-73, July-Sept. 2003.

P.Ellervee, J.Raik, V.Tihomirov. Fault Emulation on FPGA: A Feasibility Study. Proc. of the Norchip Conference, Nov. 11-12, 2003.

R.Ubar, J.Raik, B.Klüver. Algorithms for hierarchical fault simulation in digital systems. MIXDES Conference, pp. 530-535, Lodz, Poland, June 26-28, 2003.

R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In "Networks on Chip" by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. 23rd Int. Conf. on Microelectronics, Vol.2, pp.621-624, Nis, Yugoslavia, May 12-15 2002.

A.Jutman, J.Raik, R.Ubar. SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation and Test. Proc. of the 5th International Workshop on Boolean Problems. pp. 157-166, Sept. 19-20, 2002, Freiberg, Germany.

A.Schneider, E.Ivask, P.Miklos, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of Design Automation and Test in Europe - DATE02, pp. 221-226, Paris, March 4-8, 2002.

A. Schneider, K.-H. Diener, G. Elst, E. Ivask, J. Raik, R. Ubar. Internet-Based Testability-Driven Test Generation in Virtual Environment MOSCITO, Proc. of the International Workshop on IP-Based SoC Design, Oct. 30-31, 2002, Grenoble, France.

A. Schneider , K.-H. Diener , G. Jervan , Z. Peng , J. Raik ,R. Ubar , T. Hollstein , M. Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.

J. Raik, A. Jutman, R. Ubar. Exact Static Compaction of Independent Test Sequences. Proc. of the Baltic Electronic Conference, Oct. 7-9, 2002, Tallinn, Estonia.

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests using branch-and-bound and Search State Registration, IEEE European Test Workshop, Corfu, Greece, May 26-29, 2002.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the ICECS 2002 Conference. Vol. II, pp. 445-448, Sept. 15-18, 2002, Dubrovnik, Croatia.

R.Ubar, A.Jutman, E. Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. Microelectronics Education. Proc. of the 4th European Workshop on Microelectronics Education. Marcombo publishers, pp. 317-320, May 23-24, 2002, University of Vigo, Spain.

R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics, Vol.2, pp.617-620, Nis, Yugoslavia, May 12-15 2002.

R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams, IEEE Workshop on Electronic Design, Test and Applications - DELTA02, pp.86-91, Christchurch, New Zealand, 29-31 January 2002.

R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams, Proc. of the NORCHIP Conference, Nov. 11-12, 2002, Copenhagen, Denmark.

T. Cibakova, M. Fischerova, E. Gramatova, W. Kuzmicz, W.A. Pleskacz, J. Raik, R. Ubar. Hierarchical test generation for combinational circuits with real defects coverage, Journal of Microelectronics Reliability. Pergamon Press. Vol 42/7, pp 1141-1149, July 2002.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search, Digest of European Test Workshop, pp. 207-210, Stockholm, May 29 - June 1, 2001.

M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits, Proc. of 42th International Scientific Conference of Riga Technical University, pp.91-94, Riga, October 11-13, 2001.

M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements, Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, pp 2023-2040, Dec. 2001.

R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems, Proceedings of Int. Symp. on Signals, Circuits and Systems SCS 2001, pp.181-184, Iasi, Romania, July 10-11, 2001.

T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation, Proc. of the Design and Diagnostics of Electronic Circuits and Systems DDECS'2001 Conference, pp. 163-168, Györ, Hungary, April 18-20, 2001.

T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. MIXDES 01, pp.131-136, Zakopane, Poland, June 21-23, 2001.

W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits, 2nd International Symposium on Quality of Electronic Design, pp. 365-371, San Jose, California, USA, 2001

A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

A.Morawiec, R.Ubar, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. Proceedings of the DATE Conference, p. 743, Paris, France, March 27-30, 2000.

E.Ivask, J.Raik, R.Ubar. Fault-Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, pp. 319-320 Cascais, Portugal, May 23-26, 2000.

J.Raik. Greedy Alternative for the Static Compaction of Sequential Circuit Test Sequences. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

J. Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, June, 2000.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. Formal Proceedings of the IEEE European Test Workshop, pp. 69-74, Cascais, Portugal, May 23-26, 2000.

M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams, Proc. of the IEEE ISCAS'2000 Conference, Vol. 1, pp. 208-211, Geneva, Switzerland, May 28-31, 2000.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. Baltic Electronics Conference, Tallinn, Estonia, Oct. 8-11, 2000.

R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems, International Symposium on Quality of Electronic Design, pp. 189-195, San Jose, California, USA, March 20-22, 2000.

A.Markus, J.Raik, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representation, Proc. of the Second Electronic Circuits and Systems Conference ECS'99, pp. 17-20, Bratislava, Slovakia, Sept. 6-8, 1999.

G.Jervan, P.Eles, Z.Peng, J.Raik, R.Ubar. High-Level Test Synthesis with Hierarchical Test Generation, Proc. of the NORCHIP Conference, pp. 291-296, Oslo, Norway, Nov. 8-9, 1999.

J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Proc. of the European Test Workshop, pp. 84-89, Konstanz, Germany, May 25-28, 1999.

J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation, Proc. of the European Test Workshop, pp. 84-89, Konstanz, Germany, May 25-28, 1999.

J.Raik, R.Ubar. Sequential Circuit Test Generation Using Decision Diagram Models, Proceedings of the DATE Conference, pp. 736-740, Munich, Germany, March 9-12, 1999.

K.H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. FPGA Design Flow with Automated Test Generation, Proc. of the 11th Workshop on Test Technology and Reliability of Circuits and Systems, pp. 120-123, Potsdam, Germany, Feb 28-Mar 2, 1999.

R.Ubar, A.Morawiec, J.Raik. Cycle-based Simulation with Decision Diagrams, Proceedings of the DATE Conference, pp. 454-458, Munich, Germany, March 9-12, 1999.

A.Markus, J.Raik, R.Ubar. Test Set Minimization using Bipartite Graphs. Proc. of the BEC'98 Conference, pp. 175-178, Tallinn, Estonia, Oct. 7-9, 1998.

E. Ivask, J.Raik, R.Ubar. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the BEC'98 Conference, pp. 163-166, Tallinn, Estonia, Oct. 7-9, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct. 7-9, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: A Decision Diagram based Hierarchical Test Generation System. Proc. of the DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998.

G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation with Multi-Level Decision Diagram Models. Proc. of the 7-th IEEE North Atlantic Test Workshop, pp. 26-33, West Greenwich, RI, USA, May 28-29, 1998.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A CAD System for Teaching Digital Test. Microelectronics Education. Proc. of the 2nd European Workshop on Microelectronics Education, Kluwer Academic Publishers, pp. 287-290, Noordwijkerhout, the Netherlands, May 14-15, 1998.

G.Jervan, A.Markus, R.Ubar, J.Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., pp. 335-340, Lodz, Poland, June 18-20, 1998.

G.Jervan, A.Markus, R.Ubar, J.Raik. VHDL based Test Generation System. Proc. of the 5th Int. Conf. on Electronic Devices and Systems, pp. 145-148, Brno, Czech Republic, June 11-12, 1998.

J.Raik, R.Ubar. Feasibility of Structurally Synthesized BDD Models for Test Generation. Compendium of Papers of the European Test Workshop, pp. 145-146, Barcelona, May 27-29, 1998.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998.

R. Ubar, J. Heinlaid, L. Raun, J. Raik. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams. Proc. of the BEC'98 Conference, pp. 179-182, Tallinn, Estonia, Oct. 7-9, 1998.

R. Ubar, J. Raik. Hierarchical test generation for digital systems based on combining bottom-up and top-down approaches. Proc. of the World Multiconference SCI'98 / ISAS'98, pp. 374-381, Orlando, USA, July 12-16, 1998.

A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 212-216, Paris, France, October 20-22, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Assembling Low-Level Tests to High-Level Test Frames. Proc. of the IEEE 15th NORCHIP Conf. pp. 275-280, Tallinn, Estonia, Nov. 10-11, 1997.

G.Jervan, A.Markus, J.Raik, R.Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the International Conference on Design and Diagnostics of Electronic Circuits and Systems '97. pp. 35-40, Beskydy Mountains, Czech Republic, May 12-16, 1997.

M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997.

M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Mixed-Level Test Generator for Digital Systems. Proc. of the Estonian Acad. of Sci. Engng. Vol. 3, No. 4, pp. 269-280, Tallinn, Estonia, 1997.

R.Ubar, J.Raik. Multi-Valued Simulation With Binary Decision Diagrams. Compedium of Papers of IEEE European Test Workshop. pp. 28-29, Cagliari, Italy, May 28-30, 1997.

G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996.

J.Raik, P.Paomets. Test Synthesis from Register-Transfer Level Descriptions. Proc. of the 5-th Baltic Electronics Conference. pp. 311-314, Tallinn, Estonia, Oct. 1996.

J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996.

R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996.

R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb. 1996.

R.Ubar, A.Buldas, P.Paomets, J.Raik, V.Tulit. A PC-based CAD System for Training Digital Test. Proc. of the V EUROCHIP Workshop on VLSI Design Training. pp. 152-157, Dresden, Germany, Oct. 1994.

last updated: 26.09.2005

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