[ sulge aken ]
| Elulookirjeldus (CV) | ||
| 1. | Eesnimi | Gert |
| 2. | Perekonnanimi | Jervan |
| 3. | Töökoht | Tallinna Tehnikaülikool, Arvutitehnika instituut |
| 4. | Ametikoht | Erakorraline vanemteadur |
| 5. | Sünniaeg | 23.08.1974 (päev.kuu.aasta) |
| 6. | Haridus | 1998-2005 - Linköpingi Ülikool, Rootsi 1992-1998 - Tallinna Tehnikaülikool, Eesti Täiendkoolitus: 1995: TIMA Laboratories (Grenoble, Prantsusmaa): TEMPUS programmi tudeng (3 kuud). 1996: HUT (Helsingi, Soome): „Low voltage, high-speed analog and digital VLSI design” (1 nädal). 1997: Fraunhofer Institute (Dresden, Saksamaa): külalistudeng (2 kuud). |
| 7. | Teenistuskäik | Alates 15/06/2005 - Tallinna Tehnikaülikooli vanemteadur. 2005 (veebruar-juuni) - Tallinna Tehnikaülikooli teadur, 1998-2005 - Linköpingi Ülikool, Rootsi: Doktorant/teadustöö assistent (1998-2005), projektijuht (2002-2005). 1996-1998 - Tallinna Tehnikaülikool. Insener. 1994-1996 - Tallinna Kesklinna Koolidevaheline Õppekeskus. Õpetaja. |
| 8. | Teaduskraad | Tehnikateaduste doktor (Teknologie doktor) Tehnikateaduste litsensiaat (Teknologie licentiat) Tehnikateaduste magister |
| 9. | Teaduskraadi välja andnud asutus, aasta |
Linköpingi Ülikool, Rootsi, 2005 Linköpingi Ülikool, Rootsi, 2002 Tallinna Tehnikaülikool, Eesti, 1998 |
| 10. | Tunnustused | 2005 - Akadeemik Boris Tamme nimeline stipendium |
| 11. | Teadusorganisatsiooniline ja –administratiivne tegevus |
Konverentside organiseerimine: IEEE European Test Workshop 2001, Stockholm, Rootsi. Finantsjuht. Retsensenseerimine (erinevatel aastatel): IEE Proceedings Computers & Digital Techniques, Journal of Systems Architecture (Elsevier), Design, Automation and Test in Europe (DATE) konverents, International Test Conference (ITC), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), Euromicro Conference on Digital Systems Design (DSD), IEEE Workshop on Embedded System for Real-Time Multimedia (ESTIMedia), jne. IEEE liige (alates 1999), IEEE Computer Society liige (alates 1999), ACM liige (alates 2006), European Electronic Chips & Systems Initiative (ECSI) liige (alates 2002). EL temaatilise võrgustiku EIE-Surveyor juhtkomitee liige |
| 12. | Juhendamisel kaitstud väitekirjad |
Tatjana Shchenova, MSc, 2005, juh. Raimund Ubar, Gert Jervan. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Tallinna Tehnikaülikool Maksim Jenihhin, MSc, 2004, juh. Raimund Ubar, Gert Jervan. Test Time Minimization for Hybrid BIST of Systems-on-Chip. Tallinna Tehnikaülikool Yuanhui Sun, MSc, 2002, juh. Gert Jervan, Zebo Peng. Automatic Behavioral Test Generation by Using a Constraint Solver. Linköping University |
| 13. | Teadustöö põhisuunad | Digitaalsüsteemide test ja diagnostika, süsteemide isetestitavus ja veakindlus. Selles valdkonnas on avaldatud üle 30 teadusartikli, 2 raamatupeatükki ning tulemused on summeeritud kahes monograafias: High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems (2002, ISBN: 91-7373-442-X) ja Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems (2005, ISBN: 91-85297-97-6). |
| 14. | Jooksvad grandid | ETF Järeldoktor 2005-2006 ETF Grant G6829 - Kiipvõrkudel põhinevate kiipsüsteemide veakindlus ja testimine |
| 15. | Teaduspublikatsioonid |
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "A Hybrid BIST Energy Minimization Technique for System-on-Chip Testing", IEE Proceedings Computers & Digital Techniques, 2006 (accepted for publication) Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles, "An Approach to System-Level DFT", Chapter in "System-level Test and Validation of Hardware/Software Systems," Matteo Sonza Reorda, Zebo Peng, Massimo Violante (Eds.), Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, pp. 91-118, 2005 Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles, "Test Generation: A Hierarchical Approach", Chapter in "System-level Test and Validation of Hardware/Software Systems," Matteo Sonza Reorda, Zebo Peng, Massimo Violante (Eds.), Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, pp. 65-78, 2005 Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment", 10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7 Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina, "An Improved Estimation Technique for Hybrid BIST Test Set Generation", IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185 Zhiyuan He, Gert Jervan, Petru Eles, Zebo Peng, "Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, pp 83-86. Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina, "An Improved Estimation Methodology for Hybrid BIST Cost Calculation", IEEE Norchip 2004, Oslo, Norway, November 8-9, 2004, pp. 297-300 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture", The 5th IEEE Latin-American Test Workshop, Cartagena, Colombia, March 8-10, 2004, pp. 98-103 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting", The IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), Perth, Australia, January 28-30, 2004, pp. 3-8 Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles, "Hybrid BIST Test Scheduling Based on Defect Probabilities", 2004 IEEE Asian Test Symposium (ATS 2004), Kenting, Taiwan, November 15-17, 2004, pp. 230-235 Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin, "Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture", 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003, pp. 225-232 Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin, "Test Time Minimization for Hybrid BIST of Core-Based Systems", 12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 318-323 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting", The 21st NORCHIP Conference, Riga, Latvia, November 10-11, 2003, pp. 112-116 Andre Schneider, Karl-Heinz Diener, Gert Jervan, Zebo Peng, Jaan Raik, Raimund Ubar, Thomas Hollstein, Manfred Glesner, "High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory", The 8th biennial Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 287-290 Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, "High-Level and Hierarchical Test Sequence Generation", IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002, pp. 169-174 Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus, "A Hybrid BIST Architecture and its Optimization for SoC Testing", IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA, pp. 273-279 Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma, "Fast Test Cost Calculation for Hybrid BIST in Digital Systems", Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325 Raimund Ubar, Helena Kruus, Gert Jervan, Zebo Peng, "Using Tabu Search Method for Optimizing the Cost of Hybrid BIST", 16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450 Gert Jervan, Zebo Peng, Raimund Ubar, "Test Cost Minimization for Hybrid BIST", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291. Gert Jervan, Petru Eles, Zebo Peng, "A Hierarchical Test Generation Technique for Embedded Systems", Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24 Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar, "High-level Test Synthesis with Hierarchical Test Generation", IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296 Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct 7-9, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar, "DECIDER: A Decision Diagram based Hierarchical Test Generation System", DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar, "Hierarchical Test Generation with Multi-Level Decision Diagram Models", 7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. A CAD System for Teaching Digital Test. Proc. of the 2nd European Workshop on Microelectronics Education, Noordwijkerhout, the Netherlands, pp. 287-290, May 14-15, 1998. Gert Jervan, Antti Markus, Raimund Ubar, Jaan Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., Lodz, Poland, pp. 335-340, June 18-20, 1998. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar, "Hierarchical Test Generation for Digital Systems", Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Assembling Low-Level Tests to High-Level Symbolic Test Frames. Proc. of the 15th NORCHIP Conference pp. 275-281, Tallinn, Estonia, Nov. 10-11, 1997. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the Conference on Design and Diagnostics of Electronic Circuits and Systems '97. Ostrava, Czech Republic, May 12-14, 1997. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 269-280. M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996. J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996. R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996. R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb.1996. |
viimati muudetud: 18.04.2006
| Curriculum Vitae (CV) | ||
| 1. | First Name | Gert |
| 2. | Surname | Jervan |
| 3. | Institution | Tallinn University of Technology, Department of Computer Engineering |
| 4. | Position | Extraordinary senior research fellow |
| 5. | Date of birth | 23.08.1974 (day.month.year) |
| 6. | Education | 1998-2005 - Linköping University, Sweden 1992-1998 - Tallinn University of Technology, Estonia Additional studies: 1995: TIMA Laboratories (Grenoble, France): TEMPUS student (3 months). 1996: HUT (Helsinki, Finland): „Low voltage, high-speed analog and digital VLSI design” (1 week). 1997: Fraunhofer Institute (Dresden, Germany): guest student (2 months). |
| 7. | Research and professional experience |
Since June 15, 2005 - Tallinn University of Technology, senior research fellow. 2005 (Feb-June) - Tallinn University of Technology, research fellow. 1998-2005 - Linköping University, Sweden. Graduate student/research fellow (1998-2005), project manager (2002-2005) 1996-1998 - Tallinn Univerity of Technology, engineer. 1994-1996 - Tallinn Central Education Centre, teacher. |
| 8. | Academic degree | Ph.D. (Teknologie doktor) Tech. Lic. (Teknologie licentiat) M.Sc. |
| 9. | Dates and sites of earning the degrees |
Linköping University, Sweden, 2005 Linköping University, Sweden, 2002 Tallinn University of Technology, Estonia, 1998. |
| 10. | Honours/awards | 2005 - Boris Tamm postdoc scholarship |
| 11. | Research-administrative experience |
Conference organization: IEEE European Test Workshop 2001, Stockholm, Sweden. Finance Chair. Reviewer (occasionally): IEE Proceedings Computers & Digital Techniques, Journal of Systems Architecture (Elsevier), Design, Automation and Test in Europe (DATE) konverents, International Test Conference (ITC), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), Euromicro Conference on Digital Systems Design (DSD), IEEE Workshop on Embedded System for Real-Time Multimedia (ESTIMedia), and others. IEEE member (since 1999), IEEE Computer Society member (since 1999), ACM member (since 2006), European Electronic Chips & Systems Initiative (ECSI) member (since 2002). Member of the EU thematic network EIE-Surveyor Managing team |
| 12. | Supervised dissertations |
Tatjana Shchenova, MSc, 2005, superv. Raimund Ubar, Gert Jervan. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. Tallinna Tehnikaülikool Maksim Jenihhin, MSc, 2004, superv. Raimund Ubar, Gert Jervan. Test Time Minimization for Hybrid BIST of Systems-on-Chip. Tallinna Tehnikaülikool Yuanhui Sun, MSc, 2002, superv. Gert Jervan, Zebo Peng. Automatic Behavioral Test Generation by Using a Constraint Solver. Linköping University |
| 13. | Current research program | Test and diagnostics of digital systems, built-in self-test, reliability and fault tolerance. In these domains more than 30 conference papers and 2 book chapters have been published. The results have been summarized in 2 monographies: "High-Level Test Generation and Built-In Self-Test Techniques for Digital Systems" (2002, ISBN: 91-7373-442-X) and "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems" (2005, ISBN: 91-85297-97-6). |
| 14. | Current grant funding | ETF postdoc 2005-2006 ETF Grant G6829 - Test and Fault Tolerance of Network-on-Chip Based Systems |
| 15. | List of most important publications |
Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "A Hybrid BIST Energy Minimization Technique for System-on-Chip Testing", IEE Proceedings Computers & Digital Techniques, 2006 (accepted for publication) Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles, "An Approach to System-Level DFT", Chapter in "System-level Test and Validation of Hardware/Software Systems," Matteo Sonza Reorda, Zebo Peng, Massimo Violante (Eds.), Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, pp. 91-118, 2005 Gert Jervan, Raimund Ubar, Zebo Peng, Petru Eles, "Test Generation: A Hierarchical Approach", Chapter in "System-level Test and Validation of Hardware/Software Systems," Matteo Sonza Reorda, Zebo Peng, Massimo Violante (Eds.), Springer Series in Advanced Microelectronics, Vol. 17, ISBN 1-85233-899-7, pp. 65-78, 2005 Gert Jervan, Raimund Ubar, Tatjana Shchenova, Zebo Peng, "Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment", 10th IEEE European Test Symposium (ETS'05) Tallinn, Estonia, May 22-25, 2005, pp. 2-7 Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina, "An Improved Estimation Technique for Hybrid BIST Test Set Generation", IEEE Workshop on Design and Diagnostics of Electronic Circuit and Systems (DDECS), Sopron, Hungary, April 13-16, 2005, pp. 182-185 Zhiyuan He, Gert Jervan, Petru Eles, Zebo Peng, "Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment", 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, August 30 - September 3, pp 83-86. Gert Jervan, Zebo Peng, Raimund Ubar, Olga Korelina, "An Improved Estimation Methodology for Hybrid BIST Cost Calculation", IEEE Norchip 2004, Oslo, Norway, November 8-9, 2004, pp. 297-300 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture", The 5th IEEE Latin-American Test Workshop, Cartagena, Colombia, March 8-10, 2004, pp. 98-103 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting", The IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), Perth, Australia, January 28-30, 2004, pp. 3-8 Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles, "Hybrid BIST Test Scheduling Based on Defect Probabilities", 2004 IEEE Asian Test Symposium (ATS 2004), Kenting, Taiwan, November 15-17, 2004, pp. 230-235 Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin, "Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture", 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), Cambridge, MA, USA, November 3-5, 2003, pp. 225-232 Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin, "Test Time Minimization for Hybrid BIST of Core-Based Systems", 12th IEEE Asian Test Symposium (ATS03), Xian, China, November 17-19, 2003, pp. 318-323 Raimund Ubar, Maksim Jenihhin, Gert Jervan, Zebo Peng, "Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting", The 21st NORCHIP Conference, Riga, Latvia, November 10-11, 2003, pp. 112-116 Andre Schneider, Karl-Heinz Diener, Gert Jervan, Zebo Peng, Jaan Raik, Raimund Ubar, Thomas Hollstein, Manfred Glesner, "High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory", The 8th biennial Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 287-290 Gert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante, "High-Level and Hierarchical Test Sequence Generation", IEEE International Workshop on High Level Design Validation and Test, Cannes, France, October 27-29, 2002, pp. 169-174 Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus, "A Hybrid BIST Architecture and its Optimization for SoC Testing", IEEE 2002 3rd International Symposium on Quality Electronic Design (ISQED'02), March 18-20, 2002, San Jose, California, USA, pp. 273-279 Raimund Ubar, Gert Jervan, Zebo Peng, Elmet Orasson, Rein Raidma, "Fast Test Cost Calculation for Hybrid BIST in Digital Systems", Euromicro Symposium on Digital Systems Design, Warsaw, Poland, Sept. 4-6, 2001, pp. 318-325 Raimund Ubar, Helena Kruus, Gert Jervan, Zebo Peng, "Using Tabu Search Method for Optimizing the Cost of Hybrid BIST", 16th Conference on Design of Circuits and Integrated Systems (DCIS 2001), Porto, Portugal, November 20-23, 2001, pp. 445-450 Gert Jervan, Zebo Peng, Raimund Ubar, "Test Cost Minimization for Hybrid BIST", IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'2000), Yamanashi, Japan, 25-27 October, 2000, pp. 283-291. Gert Jervan, Petru Eles, Zebo Peng, "A Hierarchical Test Generation Technique for Embedded Systems", Electronic Circuits and Systems Conference, Bratislava, Slovakia, September 6-8, 1999, pages 21-24 Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar, "High-level Test Synthesis with Hierarchical Test Generation", IEEE NORCHIP Conference, Oslo, Norway, November 8-9, 1999, pages 291-296 Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. A Decision Diagram based Hierarchical Test Generator. Proc. of the BEC'98 Conference, pp. 159-162, Tallinn, Estonia, Oct 7-9, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar, "DECIDER: A Decision Diagram based Hierarchical Test Generation System", DDECS'98 Conference, pp. 269-273, Szczyrk, Poland, September 2-4, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar, "Hierarchical Test Generation with Multi-Level Decision Diagram Models", 7th IEEE North Atlantic Test Workshop, West Greenwich, RI, USA, pp. 26-33, May 28-29, 1998. Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. A CAD System for Teaching Digital Test. Proc. of the 2nd European Workshop on Microelectronics Education, Noordwijkerhout, the Netherlands, pp. 287-290, May 14-15, 1998. Gert Jervan, Antti Markus, Raimund Ubar, Jaan Raik. Mixed Level Deterministic - Random Test Generation for Digital Systems. Proc. of the MIXDES'98 Conf., Lodz, Poland, pp. 335-340, June 18-20, 1998. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar, "Hierarchical Test Generation for Digital Systems", Mixed Design of Integrated Circuits and Systems, Kluwer Academic Publishers, pp. 131-136, 1998. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Assembling Low-Level Tests to High-Level Symbolic Test Frames. Proc. of the 15th NORCHIP Conference pp. 275-281, Tallinn, Estonia, Nov. 10-11, 1997. Gert Jervan, Antti Markus, Jaan Raik, Raimund Ubar. Automatic Test Generation System for VLSI. Proc. of the 1-st Electronic Circuits and Systems Conference. pp. 255-258, Bratislava, Slovakia, Sep. 4-5, 1997. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of the Conference on Design and Diagnostics of Electronic Circuits and Systems '97. Ostrava, Czech Republic, May 12-14, 1997. Marina Brik, Gert Jervan, Antti Markus, Priidu Paomets, Jaan Raik, Raimund Ubar. Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 269-280. M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. Proc. of the 4-th International Workshop on Computer Aided Design of Modern Devices and ICs. pp. 415-420, Poznan, Poland, June 12-14, 1997. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design with Turbo Tester Software. Proc. of the 3rd Advanced Training Course: Mixed Design of Integrated Circuits and Systems MIXDES'96. pp. 589-594, Lodz, Poland, May 30 - June 1, 1996. J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate-Level Test Generator. Proc. of the 5-th Baltic Electronics Conference. pp. 237-240, Tallinn, Estonia, Oct. 1996. R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Proc. of the 5-th Baltic Electronics Conference. pp. 229-232, Tallinn, Estonia, Oct. 1996. R.Ubar, J.Raik, P.Paomets, E.Ivask, G.Jervan, A.Markus. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. pp. 185-188, Grenoble, France, Feb.1996. |
last updated: 18.04.2006
[ sulge aken ]