[ sulge aken ]

Elulookirjeldus (CV)
1.Eesnimi Artur
2.Perekonnanimi Jutman
3.Töökoht Tallinna Tehnikaülikool
4.Ametikoht Arvutitehnika Instituut, vanemteadur
5.Sünniaeg 12.01.1976 (päev.kuu.aasta)
6.Haridus 1999-2004 - Tallinna Tehikaülikool, doktoriõpe
1993-1999 - Tallinna Tehikaülikool, diplomi- ja magistriõpe
1983-1993 - Tallinna 5. Keskkool
7.Teenistuskäik 2005 - TTÜ, Arvutitehnika Instituut, vanemteadur
2001-2005 - TTÜ, Arvutitehnika Instituut, teadur
2001-2001 - TTÜ, Arvutitehnika Instituut, vaneminsener
1999-2001 - TTÜ, Arvutitehnika Instituut, insener
8.Teaduskraad tehnikateaduste doktor
tehnikateaduste magiser
9.Teaduskraadi välja
andnud asutus, aasta		 2004, Tallinna Tehikaülikool
1999, Tallinna Tehikaülikool
10.Tunnustused 2005 - Parim ettekanne EAEEIE konverentsil Lappeenrantas, Soomes
2003 - Silmapaistev artikkel MIXDES konverentsil Poolas
2000 - Eesti üliõpilaste teadustööde riikliku konkursi esimene preemia
11.Teadusorganisatsiooniline
ja –administratiivne
tegevus		 Euroopa Insnerihariduse Assotsiatsiooni EAEEIE Nõukogu liige
Muud kuuluvused assotsiatsioonidesse: IEEE
Kuulumine rahvusvaheliste konverentside teduskomiteedesse: EAEEIE
Töö retsensendina teaduskonverentsidel: DATE, ISQED, DAC, ATS, VTS, ETS, DDECS, DSD, DSN, EAEEIE, ITC, IWSBP, MIEL, MIXDES, jt.
12.Juhendamisel kaitstud
väitekirjad

Jevgeni Aleksejev, MSc, 2005, juh. Artur Jutman. Optimization of LFSR-Based TPG Using Genetic Framework. TTÜ

Dmitri Zhukov, MSc, 2004, juh. Raimund Ubar, Artur Jutman. Development of an educational environment based on DEFSIM. TTÜ
13.Teadustöö põhisuunad Ühenduste ja ühendusvõrku diagnostika, kiipvõrkude infrastruktuuri diagnostika, sisseehitatud isetestimine, binaarsed otsustusdiagrammid, testprogrammide optimeerimine.
14.Jooksvad grandid ETF: 5649, 5910
EL V Raamprogramm: IST-2001-37592 - EVIKINGS
15.Teaduspublikatsioonid

A. Jutman, “At-Speed BIST for Board-Level Interconnect”, IEEE European Board Test Workshop, Tallinn, Estonia, 25–26 May, 2005.

A. Jutman, “Efficient At-Speed Interconnect BIST and Diagnosis Framework” in Informal Digest of Papers of 10th IEEE European Test Symposium (ETS’05), Tallinn, Estonia, May 22-25, 2005, pp. 257-258.

A.Jutman, J.Raik, E.Orasson, R.Ubar, “Overview of the Educational Tools developed in REASON”, Workshop on REsearch and Training Action for System on Chip DesigN – REASON, Tallinn, May 21, 2005

A.Jutman, J.Raik, R.Ubar, V.Vislogubov, "An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform", in Proc. of 8th EUROMICRO Conference on Digital Systems Design (DSD’05), Porto, Portugal, Aug.30 – Sept. 3, 2005, pp. 412-419.

A. Jutman, M. Kruus, A. Sudnitson, R. Ubar, and H.-D. Wuttke , "Web-Based Software Package for e-Learning and Research Training in Digital System Design", in Proc. 32nd International Conference on Information Technologies in Science, Education, Telecommunication, Business (IT+SE'2005), Gurzuf, Ukraine, 2005, pp.306-308.

A. Jutman, R. Ubar, J. Raik, „Generic Interconnect BIST for Network-on-Chip”, in Proc. of 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, April 13-16, 2005, pp. 224-227.

A.Jutman, R.Ubar, J.Raik, “New Built-In Self-Test Scheme for SoC Interconnect”, in Proc of 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, Florida, USA, July 10-13, 2005, vol.4, pp.19-24.

A. Jutman, R. Ubar, V. Rosin, “A Software System for IEEE 1149.1 Boundary Scan Design, Simulation, and Demonstration”, IEEE European Board Test Workshop, Tallinn, Estonia, 25–26 May, 2005.

A.Jutman, “Testing tools”, in Handbook of Electronic Testing. Czech TU Publishing House, Prague, 2005, pp. 361-366.

A. Jutman, V. Rosin, A. Sudnitson, R. Ubar, H.-D. Wuttke, “A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard” in Proc. of 16th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering, Lappeenranta, Finland, June 6-8, 2005.

J.Raik, R.Ubar, S.Devadze, A.Jutman, “Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs”, Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York, 2005, pp. 332-344.

M. Balaz, M. Fischerova, E. Gramatova, A. Jutman, Z. Kotásek, O. Novák, T. Pikula, J. Raik, J. Strnadel, R. Ubar, J. Zahrádka, “Testing Tools for Training and Education”, in Proc. of 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’05), Krakow, June 22-25, 2005, pp.671-676.

T.Bengtsson, A.Jutman, R.Ubar, S.Kumar. “A method for crosstalk fault detection in on-chip Buses”, in Proc. of IEEE NORCHIP 2005 Conference, Oulu, Finland, Nov. 21-22, 2005, pp.285-288.

T. Bengtsson, A. Jutman, S. Kumar, R. Ubar, “Delay Testing of Asynchronous NoC Interconnects”, in Proc. of 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’05), Krakow, June 22-25, 2005, pp.419-424.

A. Jutman A. Peder J. Raik M. Tombak R. Ubar “Structurally synthesized binary decision diagrams,” in Proc. of 6th International Workshop on Boolean Problems (IWSBP’04), Freiberg, Germany, Sept. 23-24, 2004. pp. 271-278.

A. Jutman, A Sudnitson, R. Ubar, H.-D. Wuttke, “E-Learning Environment in the Area of Digital Microelectronics”, in Proc. of Int. Conf. on Information Technology Based Higher Education and Training (ITHET’04), Istanbul, Turkey, May 31 – June 2, 2004, pp. 278-283.

A. Jutman, “At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults”, in Formal Proc. of 9th IEEE European Test Symposium (ETS’04), France, 2004, pp. 2-7.

A. Jutman, “Efficient TPG for a Fast At-Speed Interconnect BIST”, in Proc. of 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’04), Stara Lesna, Slovakia, April 18-21, 2004, pp. 223-226.

A. Jutman, E. Gramatova, T. Pikula, R. Ubar, “E-Learning Tools for Teaching Self-Test of Digital Electronics”, in Proc. of 15th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, May 27-29, 2004, pp. 267-272.

A. Jutman, R. Ubar, H.-D. Wuttke, “Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems”, in Microelectronics Education, Kluwer Academic Publishers, 2004, pp.253-258

A. Jutman, Selected Issues of Modeling, Verification and Testing of Digital Systems, Tallinn University of Technology, TUT Press, Tallinn, 2004, 96 p.

A. Jutman, “Shift Register Based TPG for At-Speed Interconnect BIST”, in Proc. of 24th International Conference on Microelectronics (MIEL’04), Nis, Serbia and Montenegro, May 16-19, 2004, pp. 751-754.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke, “Research Environment for Teaching Digital Test,” in Proc. of 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473.

Jutman A., Sudnitson A., Ubar R., Wuttke H.-D, “Asynchronous E-Leaning Resources for Hardware Design Issues”, in Proc. of the International Conference on Computer Systems and Technologies (CompSysTech'2004), Sofia, Bulgaria, 2004, pp. IV.11-1-6.

R. Ubar, T. Vassiljeva, J. Raik, A. Jutman, M. Tombak, A. Peder, “Optimization of Structurally Synthesized BDDs”, in Proc of 4th IASTED Int. Conf. on Modeling, Simulation, and Optimization (MSO'04), Kauai, Hawaii, USA, August 17-19, 2004, pp. 234-240.

V.Vislogubov, A.Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar, “Diagnostic Software with WEB Interface for Teaching Purposes,” in Proc. of 9th Biennial Baltic Electronics Conference (BEC’04), Tallinn, Estonia, October 4-6, 2004, pp.255-258.

A. Jutman, A. Sudnitson, R. Ubar, “Digital Design Learning System Based on Java Applets”, in Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, August 26-28, 2003, pp.183-187.

A. Jutman, A. Sudnitson, R. Ubar, H.-D.Wuttke "Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test," in Proc. of 4th International Conference on Information Technology Based Higher Education and Training (ITHET'03), Marrakech, Morocco, July 7-9, 2003, pp. 397-401.

A. Jutman, A. Sudnitson, R. Ubar, “Web-based Applet for Teaching Boundary Scan Standard IEEE 1149.1” in Proc. of 10th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'03), Lodz, Poland, June 26-28, 2003, pp. 584-589.

A. Jutman, A. Sudnitson, R. Ubar, “Web-Based Training System for Teaching Principles of Boundary Scan Technique”, in Proc. 14th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering, Gdansk, Poland, June 16-18, 2003.

A. Jutman, “On SSBDD Model Size and Complexity”, in Proc. of 4th Electronic Circuits and Systems Conference (ECS’03), Bratislava, Slovakia, September 11-12, 2003, pp. 17-22.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.-D.Wuttke, “Turbo Tester - Diagnostic Package for Research and Training”, in Scientific-Technical Journal “Radioelectronics & Informatics”. KNURE. Vol. 3(24), 2003, pp.69-73.

S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar, “E-Learning Tools for Digital Test”, in Proc. of “Distance Learning – Educational Environment of the XXI Century” Conf., Minsk, Nov. 13-15, 2003, pp. 336-342.

A. Jutman, E. Aleksejev, R. Ubar, “A New Evolutionary-Techniques-Based Approach to Optimize Pseudo-Random TPG for Logic BIST”, Proc. of the 1st Int. Congress on Mechanical and Electrical Engineering and Technology, Varna, October 7-11, 2002, Vol. I, pp. 247-252.

A. Jutman, J. Raik, R. Ubar, “On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model,” Proc. of 23rd International Conference on Microelectronics (MIEL 2002), Nis, Yugoslavia, May 12-15, 2002, pp. 621-624.

A. Jutman, J. Raik, R. Ubar, “SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms,” in Informal Digest of 7th IEEE European Test Workshop (ETW’02), Corfu, Greece, May 26-29, 2002, pp. 345-346.

A. Jutman, J. Raik, R. Ubar, “SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test,” in Proc. of 5th International Workshop on Boolean Problems (IWSBP’02), Freiberg, Germany, Sept. 19-20, 2002, pp. 157-166.

A. Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Distance-Learning Tools for Digital Design and Test Issues,” in Proc. 29th International Conference and Scientific Discussion Club “Information Technologies in Science, Education, Telecommunications, Business” (IT+SE’2002), Yalta-Gurzuf, Ukraine, May 20-30, 2002, pp. 269-272.

A. Jutman, R. Ubar, V. Hahanov, O Skvortsova, “Practical Works for On-Line Teaching Design and Test of Digital Circuits,” in Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002), Dubrovnik, Croatia, Sept. 15-18, 2002, Vol. 3, pp. 1223-1226.

J. Raik, A. Jutman, R. Ubar, “Exact static compaction of independent test sequences,” in Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 315-318.

J. Raik, A. Jutman, R. Ubar, “Fast and Exact Static Compaction of Sequential Circuit Tests Based on Branch-and-Bound Techniques,” in Informal Digest of 7th IEEE European Test Workshop (ETW’02), Corfu, Greece, May 26-29, 2002, pp. 19-20.

J. Raik, A. Jutman, R. Ubar, "Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods" in Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002), Dubrovnik, Croatia, Sept. 15-18, 2002, Vol. 2, pp. 445-448.

R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke, “Internet-Based Software for Teaching Test of Digital Circuits,” 4th European Workshop on Microelectronics Education (EWME’02). Parador de Baiona, Spain, May 23-24, 2002, pp. 317-320.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Java Technology Based Training System for Teaching Digital Design and Test,” in Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 283-286.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Teaching Digital RT-Level Self-Test using a Java Applet,” 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, “Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test,” in Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002, pp. 699-704.

S. Devadze, A. Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Web Based Tools for Synthesis and Testing of Digital Devices”, in Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002, pp. I.91-I.96. (ISBN 954-9641-28-7)

A. Jutman, R. Ubar, “Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits,” Proc. of the Estonian Academy of Sciences, Engineering, Vol. 7/4, 2001, pp 269-288.

A. Jutman, R. Ubar, “Laboratory Training for Teaching Design and Test of Digital Circuits,” in Proc 8th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2001), Zakopane, Poland, June 21-23, 2001, pp. 521-524.

J. Raik, A. Jutman, R. Ubar, “Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms,” Proc. of 4th Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2001), Györ, Hungary, April 18-20, 2001, pp. 117-122.

J. Raik, A. Jutman, R. Ubar, “Fast Static Compaction of Test Sequences Using Implications and Greedy Search” Proc. of European Test Workshop, Stockholm, Sweden, May 29 – June 1, 2001, pp. 207-209.

R. Ubar, A. Jutman, Z. Peng, “Timing Simulation of Digital Circuits with Binary Decision Diagrams,” Proc. of DATE 2001 Conference, München, Germany, March 13-16, 2001, pp. 460-466.

A. Jutman, R. Ubar, “Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model,” Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

A. Jutman, R. Ubar, “Design Error Localization in Digital Circuits by Stuck-At Fault Test Patterns,” Proc. of IEEE 22nd International Conference on Microelectronics, Niś, Yugoslavia, May 14-17, 2000, pp.723-726.

R. Ubar, A. Jutman, “Increasing the Speed of Delay Simulation in Digital Circuits,” Proc. of 7th Baltic Electronics Conference, Tallinn, Estonia, October 8-11, 2000, pp. 31-34.

R. Ubar, A. Jutman, Z. Peng, “Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs,” Proc. of NORCHIP 2000 Conference, Turku, Finland, November 6-7, 2000, pp. 254-261.

R. Ubar, A. Jutman, “Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns,” Proc. of 6th International Conference on Mixed Design of Integrated Circuits and Systems, Kraków, Poland, June 17-19, 1999, pp. 437-442.

viimati muudetud: 28.09.2005

Curriculum Vitae (CV)
1.First Name Artur
2.Surname Jutman
3.Institution Tallinn University of Technology
4.Position Department of Computer Enginering, senior researcher
5.Date of birth 12.01.1976 (day.month.year)
6.Education 1999-2004 - Tallinn University of Technology, PhD study
1993-1999 - Tallinn University of Technology, bachelor and master study
1983-1993 - High School No. 5, Tallinn
7.Research and
professional experience		 2005 - TUT, Dept. of Comp. Engineering, senior researcher
2001-2005 - TUT, Dept. of Comp. Engineering, researcher
2001-2001 - TUT, Dept. of Comp. Engineering, senior engineer
1999-2001 - TUT, Dept. of Comp. Engineering, engineer
8.Academic degree PhD
MSc
9.Dates and sites of
earning the degrees		 2004, Tallinn Univ. of Technology
1999, Tallinn Univ. of Technology
10.Honours/awards 2005 - Best Paper Award at EAEEIE conference in Lappeenranta, Finland
2003 – Outstanding paper award at MIXDES conference in Lodz, Poland
2000 – 1st prize at the contest of student works by Estonian Ministry of Education
11.Research-administrative
experience		 Council member of the European Assotiation of Electrical and Information Engineers (EAEEIE).
Membership in other assotiations: IEEE.
Scientific Committee Member of conferences: EAEEIE.
Reviewing of conference papers: DATE, ISQED, DAC, ATS, VTS, ETS, DDECS, DSD, DSN, EAEEIE, ITC, IWSBP, MIEL, MIXDES, jt.
12.Supervised dissertations

Jevgeni Aleksejev, MSc, 2005, superv. Artur Jutman. Optimization of LFSR-Based TPG Using Genetic Framework. TTÜ

Dmitri Zhukov, MSc, 2004, superv. Raimund Ubar, Artur Jutman. Development of an educational environment based on DEFSIM. TTÜ
13.Current research program Interconnect test, NoC infrastructure test, embedded self-test, binary decision diagrams, test set optimization.
14.Current grant funding Estonian Science Foundation: 5649, 5910,
EU Framework V: IST-2001-37592 - EVIKINGS
15.List of most important publications

A. Jutman, “At-Speed BIST for Board-Level Interconnect”, IEEE European Board Test Workshop, Tallinn, Estonia, 25–26 May, 2005.

A. Jutman, “Efficient At-Speed Interconnect BIST and Diagnosis Framework” in Informal Digest of Papers of 10th IEEE European Test Symposium (ETS’05), Tallinn, Estonia, May 22-25, 2005, pp. 257-258.

A.Jutman, J.Raik, E.Orasson, R.Ubar, “Overview of the Educational Tools developed in REASON”, Workshop on REsearch and Training Action for System on Chip DesigN – REASON, Tallinn, May 21, 2005

A.Jutman, J.Raik, R.Ubar, V.Vislogubov, "An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform", in Proc. of 8th EUROMICRO Conference on Digital Systems Design (DSD’05), Porto, Portugal, Aug.30 – Sept. 3, 2005, pp. 412-419.

A. Jutman, M. Kruus, A. Sudnitson, R. Ubar, and H.-D. Wuttke , "Web-Based Software Package for e-Learning and Research Training in Digital System Design", in Proc. 32nd International Conference on Information Technologies in Science, Education, Telecommunication, Business (IT+SE'2005), Gurzuf, Ukraine, 2005, pp.306-308.

A. Jutman, R. Ubar, J. Raik, „Generic Interconnect BIST for Network-on-Chip”, in Proc. of 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), Sopron, Hungary, April 13-16, 2005, pp. 224-227.

A.Jutman, R.Ubar, J.Raik, “New Built-In Self-Test Scheme for SoC Interconnect”, in Proc of 9th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, Florida, USA, July 10-13, 2005, vol.4, pp.19-24.

A. Jutman, R. Ubar, V. Rosin, “A Software System for IEEE 1149.1 Boundary Scan Design, Simulation, and Demonstration”, IEEE European Board Test Workshop, Tallinn, Estonia, 25–26 May, 2005.

A.Jutman, “Testing tools”, in Handbook of Electronic Testing. Czech TU Publishing House, Prague, 2005, pp. 361-366.

A. Jutman, V. Rosin, A. Sudnitson, R. Ubar, H.-D. Wuttke, “A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard” in Proc. of 16th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering, Lappeenranta, Finland, June 6-8, 2005.

J.Raik, R.Ubar, S.Devadze, A.Jutman, “Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs”, Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York, 2005, pp. 332-344.

M. Balaz, M. Fischerova, E. Gramatova, A. Jutman, Z. Kotásek, O. Novák, T. Pikula, J. Raik, J. Strnadel, R. Ubar, J. Zahrádka, “Testing Tools for Training and Education”, in Proc. of 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’05), Krakow, June 22-25, 2005, pp.671-676.

T.Bengtsson, A.Jutman, R.Ubar, S.Kumar. “A method for crosstalk fault detection in on-chip Buses”, in Proc. of IEEE NORCHIP 2005 Conference, Oulu, Finland, Nov. 21-22, 2005, pp.285-288.

T. Bengtsson, A. Jutman, S. Kumar, R. Ubar, “Delay Testing of Asynchronous NoC Interconnects”, in Proc. of 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES’05), Krakow, June 22-25, 2005, pp.419-424.

A. Jutman A. Peder J. Raik M. Tombak R. Ubar “Structurally synthesized binary decision diagrams,” in Proc. of 6th International Workshop on Boolean Problems (IWSBP’04), Freiberg, Germany, Sept. 23-24, 2004. pp. 271-278.

A. Jutman, A Sudnitson, R. Ubar, H.-D. Wuttke, “E-Learning Environment in the Area of Digital Microelectronics”, in Proc. of Int. Conf. on Information Technology Based Higher Education and Training (ITHET’04), Istanbul, Turkey, May 31 – June 2, 2004, pp. 278-283.

A. Jutman, “At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults”, in Formal Proc. of 9th IEEE European Test Symposium (ETS’04), France, 2004, pp. 2-7.

A. Jutman, “Efficient TPG for a Fast At-Speed Interconnect BIST”, in Proc. of 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’04), Stara Lesna, Slovakia, April 18-21, 2004, pp. 223-226.

A. Jutman, E. Gramatova, T. Pikula, R. Ubar, “E-Learning Tools for Teaching Self-Test of Digital Electronics”, in Proc. of 15th EAEEIE Conf. on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, May 27-29, 2004, pp. 267-272.

A. Jutman, R. Ubar, H.-D. Wuttke, “Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems”, in Microelectronics Education, Kluwer Academic Publishers, 2004, pp.253-258

A. Jutman, Selected Issues of Modeling, Verification and Testing of Digital Systems, Tallinn University of Technology, TUT Press, Tallinn, 2004, 96 p.

A. Jutman, “Shift Register Based TPG for At-Speed Interconnect BIST”, in Proc. of 24th International Conference on Microelectronics (MIEL’04), Nis, Serbia and Montenegro, May 16-19, 2004, pp. 751-754.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke, “Research Environment for Teaching Digital Test,” in Proc. of 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473.

Jutman A., Sudnitson A., Ubar R., Wuttke H.-D, “Asynchronous E-Leaning Resources for Hardware Design Issues”, in Proc. of the International Conference on Computer Systems and Technologies (CompSysTech'2004), Sofia, Bulgaria, 2004, pp. IV.11-1-6.

R. Ubar, T. Vassiljeva, J. Raik, A. Jutman, M. Tombak, A. Peder, “Optimization of Structurally Synthesized BDDs”, in Proc of 4th IASTED Int. Conf. on Modeling, Simulation, and Optimization (MSO'04), Kauai, Hawaii, USA, August 17-19, 2004, pp. 234-240.

V.Vislogubov, A.Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar, “Diagnostic Software with WEB Interface for Teaching Purposes,” in Proc. of 9th Biennial Baltic Electronics Conference (BEC’04), Tallinn, Estonia, October 4-6, 2004, pp.255-258.

A. Jutman, A. Sudnitson, R. Ubar, “Digital Design Learning System Based on Java Applets”, in Proc. 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, August 26-28, 2003, pp.183-187.

A. Jutman, A. Sudnitson, R. Ubar, H.-D.Wuttke "Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test," in Proc. of 4th International Conference on Information Technology Based Higher Education and Training (ITHET'03), Marrakech, Morocco, July 7-9, 2003, pp. 397-401.

A. Jutman, A. Sudnitson, R. Ubar, “Web-based Applet for Teaching Boundary Scan Standard IEEE 1149.1” in Proc. of 10th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'03), Lodz, Poland, June 26-28, 2003, pp. 584-589.

A. Jutman, A. Sudnitson, R. Ubar, “Web-Based Training System for Teaching Principles of Boundary Scan Technique”, in Proc. 14th EAEEIE Conference on Innovation in Education for Electrical and Information Engineering, Gdansk, Poland, June 16-18, 2003.

A. Jutman, “On SSBDD Model Size and Complexity”, in Proc. of 4th Electronic Circuits and Systems Conference (ECS’03), Bratislava, Slovakia, September 11-12, 2003, pp. 17-22.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.-D.Wuttke, “Turbo Tester - Diagnostic Package for Research and Training”, in Scientific-Technical Journal “Radioelectronics & Informatics”. KNURE. Vol. 3(24), 2003, pp.69-73.

S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar, “E-Learning Tools for Digital Test”, in Proc. of “Distance Learning – Educational Environment of the XXI Century” Conf., Minsk, Nov. 13-15, 2003, pp. 336-342.

A. Jutman, E. Aleksejev, R. Ubar, “A New Evolutionary-Techniques-Based Approach to Optimize Pseudo-Random TPG for Logic BIST”, Proc. of the 1st Int. Congress on Mechanical and Electrical Engineering and Technology, Varna, October 7-11, 2002, Vol. I, pp. 247-252.

A. Jutman, J. Raik, R. Ubar, “On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model,” Proc. of 23rd International Conference on Microelectronics (MIEL 2002), Nis, Yugoslavia, May 12-15, 2002, pp. 621-624.

A. Jutman, J. Raik, R. Ubar, “SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms,” in Informal Digest of 7th IEEE European Test Workshop (ETW’02), Corfu, Greece, May 26-29, 2002, pp. 345-346.

A. Jutman, J. Raik, R. Ubar, “SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test,” in Proc. of 5th International Workshop on Boolean Problems (IWSBP’02), Freiberg, Germany, Sept. 19-20, 2002, pp. 157-166.

A. Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Distance-Learning Tools for Digital Design and Test Issues,” in Proc. 29th International Conference and Scientific Discussion Club “Information Technologies in Science, Education, Telecommunications, Business” (IT+SE’2002), Yalta-Gurzuf, Ukraine, May 20-30, 2002, pp. 269-272.

A. Jutman, R. Ubar, V. Hahanov, O Skvortsova, “Practical Works for On-Line Teaching Design and Test of Digital Circuits,” in Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002), Dubrovnik, Croatia, Sept. 15-18, 2002, Vol. 3, pp. 1223-1226.

J. Raik, A. Jutman, R. Ubar, “Exact static compaction of independent test sequences,” in Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 315-318.

J. Raik, A. Jutman, R. Ubar, “Fast and Exact Static Compaction of Sequential Circuit Tests Based on Branch-and-Bound Techniques,” in Informal Digest of 7th IEEE European Test Workshop (ETW’02), Corfu, Greece, May 26-29, 2002, pp. 19-20.

J. Raik, A. Jutman, R. Ubar, "Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods" in Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002), Dubrovnik, Croatia, Sept. 15-18, 2002, Vol. 2, pp. 445-448.

R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke, “Internet-Based Software for Teaching Test of Digital Circuits,” 4th European Workshop on Microelectronics Education (EWME’02). Parador de Baiona, Spain, May 23-24, 2002, pp. 317-320.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Java Technology Based Training System for Teaching Digital Design and Test,” in Proc. of 8th Baltic Electronics Conference (BEC 2002), Tallinn, Estonia, October 6-9, 2002, pp. 283-286.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, “Teaching Digital RT-Level Self-Test using a Java Applet,” 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, “Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test,” in Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2002), Wroclaw, Poland, June 20-22, 2002, pp. 699-704.

S. Devadze, A. Jutman, M. Kruus, A. Sudnitson, and R.Ubar, “Web Based Tools for Synthesis and Testing of Digital Devices”, in Proc. International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002, pp. I.91-I.96. (ISBN 954-9641-28-7)

A. Jutman, R. Ubar, “Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits,” Proc. of the Estonian Academy of Sciences, Engineering, Vol. 7/4, 2001, pp 269-288.

A. Jutman, R. Ubar, “Laboratory Training for Teaching Design and Test of Digital Circuits,” in Proc 8th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2001), Zakopane, Poland, June 21-23, 2001, pp. 521-524.

J. Raik, A. Jutman, R. Ubar, “Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms,” Proc. of 4th Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2001), Györ, Hungary, April 18-20, 2001, pp. 117-122.

J. Raik, A. Jutman, R. Ubar, “Fast Static Compaction of Test Sequences Using Implications and Greedy Search” Proc. of European Test Workshop, Stockholm, Sweden, May 29 – June 1, 2001, pp. 207-209.

R. Ubar, A. Jutman, Z. Peng, “Timing Simulation of Digital Circuits with Binary Decision Diagrams,” Proc. of DATE 2001 Conference, München, Germany, March 13-16, 2001, pp. 460-466.

A. Jutman, R. Ubar, “Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model,” Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

A. Jutman, R. Ubar, “Design Error Localization in Digital Circuits by Stuck-At Fault Test Patterns,” Proc. of IEEE 22nd International Conference on Microelectronics, Niś, Yugoslavia, May 14-17, 2000, pp.723-726.

R. Ubar, A. Jutman, “Increasing the Speed of Delay Simulation in Digital Circuits,” Proc. of 7th Baltic Electronics Conference, Tallinn, Estonia, October 8-11, 2000, pp. 31-34.

R. Ubar, A. Jutman, Z. Peng, “Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs,” Proc. of NORCHIP 2000 Conference, Turku, Finland, November 6-7, 2000, pp. 254-261.

R. Ubar, A. Jutman, “Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns,” Proc. of 6th International Conference on Mixed Design of Integrated Circuits and Systems, Kraków, Poland, June 17-19, 1999, pp. 437-442.

last updated: 28.09.2005

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