[ sulge aken ]
| Elulookirjeldus (CV) | ||
| 1. | Eesnimi | Peeter |
| 2. | Perekonnanimi | Ellervee |
| 3. | Töökoht | Tallinna Tehnikaülikool, arvutitehnika instituut |
| 4. | Ametikoht | professor |
| 5. | Sünniaeg | 07.12.1960 (päev.kuu.aasta) |
| 6. | Haridus | 2002: IMEC kursus (Leuven, Belgia): "How to write code for high-performance low-power multimedia applications" 1993-2000: Royal Institute of Technology (Stockholm, Rootsi), Ph.D., elektronsüsteemide disain 1995: HUT/ECDL-GETA suvekool (Helsingi, Soome): “Digital GaAs Circuit Design”1994: VLSI Design Training course on Compass Design Tools (Sophia Antipolis, Prantsusmaa) 1993: EUROCHIP kursus (Leuven, Belgia): "High-Level Digital System Design" 1990: Linköping University (Rootsi), külalistudeng 1979-1984: Tallinna Tehnikaülikool, Dipl. Eng., arvutitehnika (cum laude) |
| 7. | Teenistuskäik | September 2004: TTÜ, valitud professor Aprill-august 2001: Georgia Institute of Technology (Atlanta, USA), külalisteadur September 2000: TTÜ, valitud dotsent Aprill 2000: TTÜ, teadur 1993: Royal Institute of Technology (Stockholm, Rootsi), külalisteadur 1991: TTÜ, nooremteadur 1984: TTÜ, insener |
| 8. | Teaduskraad | Ph.D. (tehnikateaduste doktor) |
| 9. | Teaduskraadi välja andnud asutus, aasta |
Royal Institute of Technology (Stockholm, Rootsi), 2000 |
| 10. | Tunnustused | |
| 11. | Teadusorganisatsiooniline ja –administratiivne tegevus |
2004: Konverentsi Design and Test in Europe (DATE'05) teema "System Level Specification" programmikomitee kaasesimees 2002-2006: Konverentsi DATE teema "System Level Specification" programmikomitee liige 2003-2005: NORCHIP Conference, korralduskomitee liige 2000: Konverentsi Forum on Design Languages seminari SSDL programmikomitee liige alates 1996: eelretsenseerija teaduskonverentsidel DAC'00-DAC'06, DATE'03-DATE'06, ISQED'06, ESTIMedia'05, SoC'05, BEC'00-BEC'04, FPL'03, DSD'02, ECCDT'01, FDL'00 (lisaks kolm varasemat konverentsi) alates 2000: IEEE, Circuits and Systems Society, liige alates 2005: IEEE, Computer Society, liige aegajalt: ajakirjade JAS (03, 05), ELL (05), TVLSI (05), CDT (04), TCAD (04), ISMVL (04) artiklite eelretsenseerija |
| 12. | Juhendamisel kaitstud väitekirjad |
Allan Aasmaa, MSc, 2005, juh. Peeter Ellervee. Heuristilised algoritmid kaalutud graafide tükeldamiseks [Heuristic Algorithms for Weighted Graph Partitioning]. TTÜ, Tallinn Anton Arhipov, MSc, 2005, juh. Peeter Ellervee. VHDL Front-end for Logic Synthesis. TTÜ, Tallinn Indrek Roosileht, MSc, 2005, juh. Peeter Ellervee. Algoritmide tükeldamine kaalutud graafide abil [Partitioning of algorithms using weighted graphs]. TTÜ, Tallinn Uljana Reinsalu, MSc, 2005, juh. Peeter Ellervee. Self-organizing maps in hardware synthesis. TTÜ, Tallinn Tarmo Klaar, MSc, 2002, juh. Peeter Ellervee. Kiired heuristilised algoritmid kaalutud graafide värvimiseks [Fast Heuristic Algorithms for Weighted Graph Coloring]. TTÜ, Tallinn Johann Sällemark, MSc, 1997, juh. Thomas Hollstein, Peeter Ellervee. Enhancement of a Generic Fuzzy System by Additional VHDL Modules. KTH, Stockholm / DTU, Darmstadt Bengt Svantesson, MSc, 1996, juh. Ahmed Hemani, Peeter Ellervee. Modelling of OAM for ATM in VHDL. KTH, Stockholm David Dong, MSc, 1996, juh. Ahmed Hemani, Peeter Ellervee. Benchmark Library for High-Level Synthesis Tools. KTH, Stockholm |
| 13. | Teadustöö põhisuunad | Kiipsüsteemi disain; arhitektuurne ja kõrgtasemesüntees; loogika-taseme süntees; riist- ja tarkvara koosdisain; riistvara kirjelduskeeled |
| 14. | Jooksvad grandid | ETF grant 5601 "Digitaalsüsteemide käitumuslik ja funktsionaalne tükeldamine" (2003-2005) |
| 15. | Teaduspublikatsioonid |
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar, "Improved Fault Emulation for Synchronous Sequential Circuits." The 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, pp.72-78, Aug. 2005. J. Öberg, J. Plosila, P. Ellervee, "Automatic Synthesis of Asynchronous Circuits from Synchronous RTL Descriptions." The 23rd NORCHIP Conference, Oulu, Finland, pp.200-205, Nov. 2005. E. Dubrova, P. Ellervee, D.M. Miller, J.C. Muzio and A.J. Sullivan, "TOP: an algorithm for three-level combinational logic optimisation." IEE Proceedings - Circuits Devices and Systems, Vol.151, No.4, pp.307-314, Aug. 2004. E. Fomina, P. Ellervee, M. Kruus, A. Sudnitson, and K. Tammemae, "Digital synthesis tools for education and research." The 18th International Conference on Systems for Automation of Engineering and Research (SAER'2004), Varna, Bulgaria, 2004. E. Ivask, P. Ellervee, "VHDL Front-End for High-Level Synthesis Tool xTractor." The 9th Biennial Baltic Electronic Conference (BEC'2004), Tallinn, Estonia, pp.111-114, Oct. 2004. J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar, "Fast Fault Emulation for Synchronous Sequential Circuits." East-West Design & Test Workshop (EWDTW'04), Yalta, Ukraine, pp.35-40, Sept. 2004. P. Ellervee, J. Raik, V. Tihhomirov, "Environment for Fault Simulation Acceleration on FPGA." The 9th Biennial Baltic Electronic Conference (BEC'2004), Tallinn, Estonia, pp.217-220, Oct. 2004. P. Ellervee, J. Raik, V. Tihhomirov, K. Tammemäe, "Evaluating Fault Emulation on FPGA." The International Conference on Field Programmable Logic and Applications (FPL'2004), Antwerp, Belgium, pp.354-363, Aug. 2004. Lecture Notes in Computer Science 3203, Springer-Verlag 2004. P. Ellervee, J. Raik, V. Tihhomirov, R. Ubar, "FPGA Based Fault Emulation of Synchronous Sequential Circuits." The 22nd NORCHIP Conference, Oslo, Norway, pp.59-62, Nov. 2004. P. Ellervee, J. Raik, V. Tihhomirov, "Fault Emulation on FPGA: A Feasibility Study." The 21st NORCHIP Conference, Riga, Latvia, pp.92-95, Nov. 2003. K. Puttaswamy, K.-W. Choi, J. C. Park, V. Mooney, A. Chatterjee, P. Ellervee, "System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-chip Buses and Memory." The 15th International Symposium on System Synthesis (ISSS'2002), pp.225-230, Kyoto, Japan, Oct. 2002. K. Puttaswamy, L. N. Chakrapani, K. W. Choi, Y. S. Dhillon, U. Diril, P. Korkmaz, K. K. Lee, J. C. Park, A. Chatterjee, P. Ellervee, V. Mooney, K. Palem and W. F. Wong, "Power-Performance Trade-Offs in second level memory used by an ARM-Like RISC Architecture." In Rami Melhem, editor, Power Aware Computing, chapter 11, pp.211-224. Kluwer Academic/Plenum Publishers, 2002. P. Ellervee, T. Klaar, M. Kruus, K. Tammemäe, "Using Weighted Graphs for Fast Architecture Exploration." The 8th Biennial Baltic Electronic Conference (BEC'2002), pp.111-114, Tallinn, Estonia, Oct. 2002. P. Ellervee, "xTractor: An Academic High-Level Synthesis Tool for Control and Memory Intensive Applications." The 20th NORCHIP Conference, Copenhagen, Denmark, pp., 253-258, Nov. 2002. A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, A. Hemani, P. Ellervee, and M. O'Nils, "A comparison of six languages for system level description of telecom applications." In Jean Mermet, editor, Electronic Chips & System Design Languages, chapter 15, pp.181-192. Kluwer Academic Publisher, 2001. M. Kruus, K. Tammemäe, P. Ellervee, "SoC Curricula at Tallinn Technical University." The 19th NORCHIP Conference, pp.99-104, Stockholm, Sweden, Nov. 2001. P. Ellervee, H. Tenhunen, "Digital Hardware Organization Course for SoC Program." 2001 International Conference on Microelectronic Systems Education (MSE'2001), pp.26-27, Las Vegas, USA, June 2001. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "System-level Data-Format Exploration for Dynamically Allocated Data Structures." IEEE Transactions on CAD, Vol. 20, No. 12, pp.1469-1472, Dec. 2001. P. Ellervee, T. Klaar, "Using Weighted Graph Coloring Heuristics for Architecture Exploration." The 19th NORCHIP Conference, pp.161-166, Stockholm, Sweden, Nov. 2001. E. Dubrova, P. Ellervee, J. Muzio, M. Miller, "TOP: An Algorithm for Three-Level Optimization of PLDs." Design and Test in Europe (D.A.T.E.), pp.751, Paris, France, March 2000. E. Ivask, P. Ellervee, "Mapping of VHDL Structures for Generic EDA Database Format IRSYD." The 7th Biennial Baltic Electronic Conference (BEC'2000), pp.317-320, Tallinn, Estonia, Oct. 2000. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "System-level Data Format Exploration for Dynamically Allocated Data Structures." The 37th Design Automation Conference (DAC'2000), pp.556-559, Los Angeles, CA, USA, June 2000. A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Öberg, P. Ellervee, D. Lundqvist, "Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style." The 36th Design Automation Conference (DAC'99), pp.873-878, New Orleans, LA, USA, June 1999. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "Exploiting Data Transfer Locality in Memory Mapping." Proceedings of the 25th Euromicro Conference, pp.14-21, Milan, Italy, Sept. 1999. T. Meincke, A. Hemani, S. Kumar, P. Ellervee, J. Öberg, T. Olsson, P. Nilsson, D. Lindqvist, H. Tenhunen, "Globally Asynchronous Locally Synchronous VLSI Architecture for large high-performance ASICs." International Symposium on Circuits and Systems (ISCAS'99), vol.II, pp.512-515, Orlando, Florida, USA, May 1999. T. Meincke, A. Jantsch, P. Ellervee, A. Hemani, H. Tenhunen, "A Generic Scheme for Communication Representation and Mapping." The 17th NORCHIP Conference, pp.334-339, Oslo, Norway, Nov. 1999. J. Öberg, P. Ellervee, A. Hemani, "Grammar-based Modelling of Clock Protocols for Low Power Implementations: A Case Study." The 16th NORCHIP Conference, pp.144-153, Lund, Sweden, Nov. 1998. J. Öberg, P. Ellervee "Revolver: A High-Performance MIMD Architecture for Collision Free Computing." The 24th Euromicro Conference, pp.301-308, Västerås, Sweden, Aug. 1998. M. Mokhtari, P. Ellervee, G. Schuppener, T. Juhola, H. Tenhunen, A. Djupsjöbacka, "Gb/s Encoder/Decoder Circuits for Fiber Optical Links in Si-Bipolar Technology." International Symposium on Circuits and Systems (ISCAS'98), pp.345-348, Monterey, USA, May 1998. P. Ellervee, S. Kumar, A. Jantsch, B. Svantesson, T. Meincke, A. Hemani, "IRSYD: An Internal Representation for Heterogeneous Embedded Systems." The 16th NORCHIP Conference, pp.214-221, Lund, Sweden, Nov. 1998. T. Meincke, A. Hemani, P. Ellervee, J. Öberg, S. Kumar, D. Lindqvist, H. Tenhunen, A. Postula, "Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI Architecture." The 16th NORCHIP Conference, pp.50-57, Lund, Sweden, Nov. 1998. J. Öberg, P. Ellervee, A. Kumar, A. Hemani, "Comparing Conventional HLS with Grammar-Based Hardware Synthesis: A Case Study." The 15th NORCHIP Conference, pp.52-59, Nov. 1997, Tallinn, Estonia. M. Mokhtari, P. Ellervee, G. Schuppener, T. Juhola, H. Tenhunen, A. Djupsjöbacka, "Encoder/Decoder for Channel-Coding in Fiber Optical Links for Gb/s Transmission Rates in Si-Bipolar Technology." The 15th NORCHIP Conference, pp.304-310, Tallinn, Estonia, Nov. 1997. P. Ellervee, S. Kumar, A. Hemani, "Comparision of Four Heuristic Algorithms for Unified Allocation and Binding in High-Level Synthesis." The 15th NORCHIP Conference, pp.60-66, Tallinn, Estonia, Nov. 1997. B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Hemani, "A Novel Allocation Strategy for Control and Memory Intensive Telecommunication Circuits." The 9th International Conference on VLSI Design, pp.23-28, Bangalore, India, Jan. 1996. J. Öberg, J. Isoaho, P. Ellervee, A. Jantsch, A. Hemani, "A Rule-Based Allocator for Improving Allocation of Filter Structures in HLS." The 9th International Conference on VLSI Design, pp.133-139, Bangalore, India, Jan. 1996. P. Ellervee, A. Hemani, A. Kumar, B. Svantesson, J. Öberg, H. Tenhunen, "Controller Synthesis in Control and Memory Centric High Level Synthesis System." The 5th Biennial Baltic Electronic Conference, pp.397-400, Tallinn, Estonia, Oct. 1996. P. Ellervee, A. Kumar, B. Svantesson, A. Hemani, "Internal Representation and Behavioural Synthesis of Control Dominated Applications." The 14th NORCHIP Conference, pp.142-149, Helsinki, Finland, Nov. 1996. P. Ellervee, A. Kumar, B. Svantesson, A. Hemani, "Segment-Based Scheduling of Control Dominated Applications in High Level Synthesis." International Workshop on Logic and Architecture Synthesis, pp.337-344, Grenoble, France, Dec. 1996. A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "High-Level Synthesis of Control and Memory Intensive Communications System." Eighth Annual IEEE International ASIC Conference and Exhibit (ASIC'95), pp.185-191, Austin, USA, Sept. 1995. A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "Trade-offs in High-level Synthesis of Telecommunication Systems." The Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'95), pp.65-72, Nara, Japan, Aug. 1995. B. Svantesson, A. Hemani, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "Modelling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics." The 13th NORCHIP Conference, pp.115-122, Copenhagen, Denmark, Nov. 1995. A. Jantsch, P. Ellervee, J. Öberg, A. Hemani, "A Case Study on Hardware/Software Partitioning." IEEE Workshop on FPGAs for Custom Computing machines (FCCM'94), pp.226-233, April, 1994. A. Jantsch, P. Ellervee, J. Öberg, A. Hemani, H. Tenhunen, "Hardware-Software Partitioning and Minimizing Memory Interface Traffic." In Proc. of the European Design Automation Conference (Euro-DAC'94), pp.226-231, Grenoble, France, Sept. 1994. P. Ellervee, A. Jantsch, J. Öberg, A. Hemani, H. Tenhunen, "Exploring ASIC Design Space At System Level with a Neural Network Estimator." Seventh Annual IEEE International ASIC Conference and Exhibit, (ASIC'94), pp.67-70, Rochester, USA, Sept. 1994. P. Ellervee, J. Öberg, A. Jantsch, A. Hemani, "Neural Network Based Estimator to Explore the Design Space at System Level." The 4th Biennial Baltic Electronic Conference, pp.391-396, Tallinn, Estonia, Oct. 1994. |
viimati muudetud: 08.02.2006
| Curriculum Vitae (CV) | ||
| 1. | First Name | Peeter |
| 2. | Surname | Ellervee |
| 3. | Institution | Tallinn University of Technology, Department of Computer Engineering |
| 4. | Position | Professor |
| 5. | Date of birth | 07.12.1960 (day.month.year) |
| 6. | Education | 2002: IMEC course (Leuven, Belgium): "How to write code for high-performance low-power multimedia applications" 1993-2000: Royal Institute of Technology (Stockholm, Sweden), Ph.D., Electronic System Design 1995: HUT/ECDL-GETA summer school (Helsinki, FI): Digital GaAs Circuit Design1994: VLSI Design Training course on Compass Design Tools (Sophia Antipolis,F) 1993: EUROCHIP course (Leuven, B): "High-Level Digital System Design" 1990: Linköping University (Sweden), guest student 1979-1984: Tallinn Technical University, Dipl. Eng., Computer Eng. (cum laude) |
| 7. | Research and professional experience |
September 2004: TUT, professor (elected) April-August 2001: Georgia Institute of Technology (Atlanta,USA), guest researcher September 2000: TTU, assoc. prof. (elected) April 2000: TTU, researcher 1993: Royal Institute of Technology (Stockholm, Sweden), guest researcher 1991: TTU, junior researcher 1984: TTU, engineer |
| 8. | Academic degree | Ph.D. |
| 9. | Dates and sites of earning the degrees |
Royal Institute of Technology (Stockholm, Sweden), 2000 |
| 10. | Honours/awards | |
| 11. | Research-administrative experience |
2004: Conf. "Design and Test in Europe" (DATE'05), topic "System Level Specification", co-chair of the program committee 2002-2006: Conf. DATE, topic "System Level Specification", member of the program committee 2003-2005: NORCHIP Conference, member of the management committee 2000: Conf. Forum on Design Languages, workshop SSDL, member of the program committee since 1996: reviewer for conferences DAC'00-DAC'06, DATE'03-DATE'06, ISQED'06, ESTIMedia'05, SoC'05, BEC'00-BEC'04, FPL'03, DSD'02, ECCDT'01, FDL'00 (plus three older conferences) since 2000: IEEE, Circuits and Systems Society, member since 2005: IEEE, Computer Society, member occasionally: reviewer for journals JAS (03, 05), ELL (05), TVLSI (05), CDT (04), TCAD (04), ISMVL (04) |
| 12. | Supervised dissertations |
Allan Aasmaa, MSc, 2005, superv. Peeter Ellervee. Heuristilised algoritmid kaalutud graafide tükeldamiseks [Heuristic Algorithms for Weighted Graph Partitioning]. TTÜ, Tallinn Anton Arhipov, MSc, 2005, superv. Peeter Ellervee. VHDL Front-end for Logic Synthesis. TTÜ, Tallinn Indrek Roosileht, MSc, 2005, superv. Peeter Ellervee. Algoritmide tükeldamine kaalutud graafide abil [Partitioning of algorithms using weighted graphs]. TTÜ, Tallinn Uljana Reinsalu, MSc, 2005, superv. Peeter Ellervee. Self-organizing maps in hardware synthesis. TTÜ, Tallinn Tarmo Klaar, MSc, 2002, superv. Peeter Ellervee. Kiired heuristilised algoritmid kaalutud graafide värvimiseks [Fast Heuristic Algorithms for Weighted Graph Coloring]. TTÜ, Tallinn Johann Sällemark, MSc, 1997, superv. Thomas Hollstein, Peeter Ellervee. Enhancement of a Generic Fuzzy System by Additional VHDL Modules. KTH, Stockholm / DTU, Darmstadt Bengt Svantesson, MSc, 1996, superv. Ahmed Hemani, Peeter Ellervee. Modelling of OAM for ATM in VHDL. KTH, Stockholm David Dong, MSc, 1996, superv. Ahmed Hemani, Peeter Ellervee. Benchmark Library for High-Level Synthesis Tools. KTH, Stockholm |
| 13. | Current research program | System-on-a-Chip design; architectural and high-level synthesis; logic level synthesis; hard- and software codesign; hardware description languages |
| 14. | Current grant funding | ESF grant 5601 "Behavioral and Functional Partitioning of Digital Systems" (2003-2005) |
| 15. | List of most important publications |
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar, "Improved Fault Emulation for Synchronous Sequential Circuits." The 8th Euromicro Conference on Digital System Design (DSD'2005), Porto, Portugal, pp.72-78, Aug. 2005. J. Öberg, J. Plosila, P. Ellervee, "Automatic Synthesis of Asynchronous Circuits from Synchronous RTL Descriptions." The 23rd NORCHIP Conference, Oulu, Finland, pp.200-205, Nov. 2005. E. Dubrova, P. Ellervee, D.M. Miller, J.C. Muzio and A.J. Sullivan, "TOP: an algorithm for three-level combinational logic optimisation." IEE Proceedings - Circuits Devices and Systems, Vol.151, No.4, pp.307-314, Aug. 2004. E. Fomina, P. Ellervee, M. Kruus, A. Sudnitson, and K. Tammemae, "Digital synthesis tools for education and research." The 18th International Conference on Systems for Automation of Engineering and Research (SAER'2004), Varna, Bulgaria, 2004. E. Ivask, P. Ellervee, "VHDL Front-End for High-Level Synthesis Tool xTractor." The 9th Biennial Baltic Electronic Conference (BEC'2004), Tallinn, Estonia, pp.111-114, Oct. 2004. J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar, "Fast Fault Emulation for Synchronous Sequential Circuits." East-West Design & Test Workshop (EWDTW'04), Yalta, Ukraine, pp.35-40, Sept. 2004. P. Ellervee, J. Raik, V. Tihhomirov, "Environment for Fault Simulation Acceleration on FPGA." The 9th Biennial Baltic Electronic Conference (BEC'2004), Tallinn, Estonia, pp.217-220, Oct. 2004. P. Ellervee, J. Raik, V. Tihhomirov, K. Tammemäe, "Evaluating Fault Emulation on FPGA." The International Conference on Field Programmable Logic and Applications (FPL'2004), Antwerp, Belgium, pp.354-363, Aug. 2004. Lecture Notes in Computer Science 3203, Springer-Verlag 2004. P. Ellervee, J. Raik, V. Tihhomirov, R. Ubar, "FPGA Based Fault Emulation of Synchronous Sequential Circuits." The 22nd NORCHIP Conference, Oslo, Norway, pp.59-62, Nov. 2004. P. Ellervee, J. Raik, V. Tihhomirov, "Fault Emulation on FPGA: A Feasibility Study." The 21st NORCHIP Conference, Riga, Latvia, pp.92-95, Nov. 2003. K. Puttaswamy, K.-W. Choi, J. C. Park, V. Mooney, A. Chatterjee, P. Ellervee, "System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-chip Buses and Memory." The 15th International Symposium on System Synthesis (ISSS'2002), pp.225-230, Kyoto, Japan, Oct. 2002. K. Puttaswamy, L. N. Chakrapani, K. W. Choi, Y. S. Dhillon, U. Diril, P. Korkmaz, K. K. Lee, J. C. Park, A. Chatterjee, P. Ellervee, V. Mooney, K. Palem and W. F. Wong, "Power-Performance Trade-Offs in second level memory used by an ARM-Like RISC Architecture." In Rami Melhem, editor, Power Aware Computing, chapter 11, pp.211-224. Kluwer Academic/Plenum Publishers, 2002. P. Ellervee, T. Klaar, M. Kruus, K. Tammemäe, "Using Weighted Graphs for Fast Architecture Exploration." The 8th Biennial Baltic Electronic Conference (BEC'2002), pp.111-114, Tallinn, Estonia, Oct. 2002. P. Ellervee, "xTractor: An Academic High-Level Synthesis Tool for Control and Memory Intensive Applications." The 20th NORCHIP Conference, Copenhagen, Denmark, pp., 253-258, Nov. 2002. A. Jantsch, S. Kumar, I. Sander, B. Svantesson, J. Öberg, A. Hemani, P. Ellervee, and M. O'Nils, "A comparison of six languages for system level description of telecom applications." In Jean Mermet, editor, Electronic Chips & System Design Languages, chapter 15, pp.181-192. Kluwer Academic Publisher, 2001. M. Kruus, K. Tammemäe, P. Ellervee, "SoC Curricula at Tallinn Technical University." The 19th NORCHIP Conference, pp.99-104, Stockholm, Sweden, Nov. 2001. P. Ellervee, H. Tenhunen, "Digital Hardware Organization Course for SoC Program." 2001 International Conference on Microelectronic Systems Education (MSE'2001), pp.26-27, Las Vegas, USA, June 2001. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "System-level Data-Format Exploration for Dynamically Allocated Data Structures." IEEE Transactions on CAD, Vol. 20, No. 12, pp.1469-1472, Dec. 2001. P. Ellervee, T. Klaar, "Using Weighted Graph Coloring Heuristics for Architecture Exploration." The 19th NORCHIP Conference, pp.161-166, Stockholm, Sweden, Nov. 2001. E. Dubrova, P. Ellervee, J. Muzio, M. Miller, "TOP: An Algorithm for Three-Level Optimization of PLDs." Design and Test in Europe (D.A.T.E.), pp.751, Paris, France, March 2000. E. Ivask, P. Ellervee, "Mapping of VHDL Structures for Generic EDA Database Format IRSYD." The 7th Biennial Baltic Electronic Conference (BEC'2000), pp.317-320, Tallinn, Estonia, Oct. 2000. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "System-level Data Format Exploration for Dynamically Allocated Data Structures." The 37th Design Automation Conference (DAC'2000), pp.556-559, Los Angeles, CA, USA, June 2000. A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Öberg, P. Ellervee, D. Lundqvist, "Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style." The 36th Design Automation Conference (DAC'99), pp.873-878, New Orleans, LA, USA, June 1999. P. Ellervee, M. Miranda, F. Catthoor, A. Hemani, "Exploiting Data Transfer Locality in Memory Mapping." Proceedings of the 25th Euromicro Conference, pp.14-21, Milan, Italy, Sept. 1999. T. Meincke, A. Hemani, S. Kumar, P. Ellervee, J. Öberg, T. Olsson, P. Nilsson, D. Lindqvist, H. Tenhunen, "Globally Asynchronous Locally Synchronous VLSI Architecture for large high-performance ASICs." International Symposium on Circuits and Systems (ISCAS'99), vol.II, pp.512-515, Orlando, Florida, USA, May 1999. T. Meincke, A. Jantsch, P. Ellervee, A. Hemani, H. Tenhunen, "A Generic Scheme for Communication Representation and Mapping." The 17th NORCHIP Conference, pp.334-339, Oslo, Norway, Nov. 1999. J. Öberg, P. Ellervee, A. Hemani, "Grammar-based Modelling of Clock Protocols for Low Power Implementations: A Case Study." The 16th NORCHIP Conference, pp.144-153, Lund, Sweden, Nov. 1998. J. Öberg, P. Ellervee "Revolver: A High-Performance MIMD Architecture for Collision Free Computing." The 24th Euromicro Conference, pp.301-308, Västerås, Sweden, Aug. 1998. M. Mokhtari, P. Ellervee, G. Schuppener, T. Juhola, H. Tenhunen, A. Djupsjöbacka, "Gb/s Encoder/Decoder Circuits for Fiber Optical Links in Si-Bipolar Technology." International Symposium on Circuits and Systems (ISCAS'98), pp.345-348, Monterey, USA, May 1998. P. Ellervee, S. Kumar, A. Jantsch, B. Svantesson, T. Meincke, A. Hemani, "IRSYD: An Internal Representation for Heterogeneous Embedded Systems." The 16th NORCHIP Conference, pp.214-221, Lund, Sweden, Nov. 1998. T. Meincke, A. Hemani, P. Ellervee, J. Öberg, S. Kumar, D. Lindqvist, H. Tenhunen, A. Postula, "Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI Architecture." The 16th NORCHIP Conference, pp.50-57, Lund, Sweden, Nov. 1998. J. Öberg, P. Ellervee, A. Kumar, A. Hemani, "Comparing Conventional HLS with Grammar-Based Hardware Synthesis: A Case Study." The 15th NORCHIP Conference, pp.52-59, Nov. 1997, Tallinn, Estonia. M. Mokhtari, P. Ellervee, G. Schuppener, T. Juhola, H. Tenhunen, A. Djupsjöbacka, "Encoder/Decoder for Channel-Coding in Fiber Optical Links for Gb/s Transmission Rates in Si-Bipolar Technology." The 15th NORCHIP Conference, pp.304-310, Tallinn, Estonia, Nov. 1997. P. Ellervee, S. Kumar, A. Hemani, "Comparision of Four Heuristic Algorithms for Unified Allocation and Binding in High-Level Synthesis." The 15th NORCHIP Conference, pp.60-66, Tallinn, Estonia, Nov. 1997. B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Hemani, "A Novel Allocation Strategy for Control and Memory Intensive Telecommunication Circuits." The 9th International Conference on VLSI Design, pp.23-28, Bangalore, India, Jan. 1996. J. Öberg, J. Isoaho, P. Ellervee, A. Jantsch, A. Hemani, "A Rule-Based Allocator for Improving Allocation of Filter Structures in HLS." The 9th International Conference on VLSI Design, pp.133-139, Bangalore, India, Jan. 1996. P. Ellervee, A. Hemani, A. Kumar, B. Svantesson, J. Öberg, H. Tenhunen, "Controller Synthesis in Control and Memory Centric High Level Synthesis System." The 5th Biennial Baltic Electronic Conference, pp.397-400, Tallinn, Estonia, Oct. 1996. P. Ellervee, A. Kumar, B. Svantesson, A. Hemani, "Internal Representation and Behavioural Synthesis of Control Dominated Applications." The 14th NORCHIP Conference, pp.142-149, Helsinki, Finland, Nov. 1996. P. Ellervee, A. Kumar, B. Svantesson, A. Hemani, "Segment-Based Scheduling of Control Dominated Applications in High Level Synthesis." International Workshop on Logic and Architecture Synthesis, pp.337-344, Grenoble, France, Dec. 1996. A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "High-Level Synthesis of Control and Memory Intensive Communications System." Eighth Annual IEEE International ASIC Conference and Exhibit (ASIC'95), pp.185-191, Austin, USA, Sept. 1995. A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "Trade-offs in High-level Synthesis of Telecommunication Systems." The Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI'95), pp.65-72, Nara, Japan, Aug. 1995. B. Svantesson, A. Hemani, P. Ellervee, A. Postula, J. Öberg, A. Jantsch, H. Tenhunen, "Modelling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics." The 13th NORCHIP Conference, pp.115-122, Copenhagen, Denmark, Nov. 1995. A. Jantsch, P. Ellervee, J. Öberg, A. Hemani, "A Case Study on Hardware/Software Partitioning." IEEE Workshop on FPGAs for Custom Computing machines (FCCM'94), pp.226-233, April, 1994. A. Jantsch, P. Ellervee, J. Öberg, A. Hemani, H. Tenhunen, "Hardware-Software Partitioning and Minimizing Memory Interface Traffic." In Proc. of the European Design Automation Conference (Euro-DAC'94), pp.226-231, Grenoble, France, Sept. 1994. P. Ellervee, A. Jantsch, J. Öberg, A. Hemani, H. Tenhunen, "Exploring ASIC Design Space At System Level with a Neural Network Estimator." Seventh Annual IEEE International ASIC Conference and Exhibit, (ASIC'94), pp.67-70, Rochester, USA, Sept. 1994. P. Ellervee, J. Öberg, A. Jantsch, A. Hemani, "Neural Network Based Estimator to Explore the Design Space at System Level." The 4th Biennial Baltic Electronic Conference, pp.391-396, Tallinn, Estonia, Oct. 1994. |
last updated: 08.02.2006
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