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Elulookirjeldus (CV)
1.Eesnimi Margit
2.Perekonnanimi Aarna
3.Töökoht Tallinna Tehnikaülikooli Arvutitehnika instituut
4.Ametikoht teadur
5.Sünniaeg 09.10.1973 (päev.kuu.aasta)
6.Haridus 2001, Tallinna Tehnikaülikool, tehnikateaduste magister
2000, Tallinna Tehnikaülikool, Arvuti- ja süsteemitehnika õppevaldkond
1992, Tallinna 13. Keskkool
7.Teenistuskäik 1.09.2003 - ..., Tallinna Tehnikaülikool, teadur
01.01. - 31.08.2003, Tallinna Tehnikaülikool, insener
2000 - 2003, Tallinna Tehnikaülikool, osalemine teadusprojektides
8.Teaduskraad Tehnikateaduste magister
9.Teaduskraadi välja
andnud asutus, aasta
Tallinna Tehnikaülikool, 2001
10.Tunnustused 2004, Tiigriülikooli stipendium IKT doktorandile
2005, Tiigriülikooli stipendium IKT doktorandile
11.Teadusorganisatsiooniline
ja –administratiivne
tegevus
12.Juhendamisel kaitstud
väitekirjad
13.Teadustöö põhisuunad Digitaalsüsteemide rikkesimuleerimisalgoritmid
14.Jooksvad grandid 5637, Kõrgtaseme testigenereerimine ja testitavuse analüüs digitaalskeemidele, J. Raik
15.Teaduspublikatsioonid

R. Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004, Vol. 2, pp. 459-462, Sinaia, Romania, Oct. 4-6, 2004.

R.Ubar, M.Aarna, M.Brik, J.Raik. High-Level Fault Modeling in Digital Systems. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 486-491, Ilmenau, Germany, September 27-30, 2004.

R.Ubar, M.Aarna, M.Brik, T.Evartson, J.Raik. High Level Fault Models for Digital Systems. In "University Research, Industry, International Cooperation", Minsk, 2004 pp.303-310.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester - Diagnostic Package for Research and Training. J. of Radioelectronics and Informatics, No3 (24), July - September, 2003, pp. 69-73.

M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits, Proc. of 42th International Scientific Conference of Riga Technical University, pp.91-94, Riga, October 11-13, 2001.

viimati muudetud: 03.08.2005

Curriculum Vitae (CV)
1.First Name Margit
2.Surname Aarna
3.Institution Tallinn University of Technology, Department of Computer Engineering
4.Position researcher
5.Date of birth 09.10.1973 (day.month.year)
6.Education 2001, Tallinn University of Technology, MSc
2000, Tallinn University of Technology, Diploma of Computer and Systems Engineering
1992, Tallinn Secondary School No. 13
7.Research and
professional experience
1.09.2003 - ... - Tallinn University of Technology - researcher
01.01. - 31.08.2003 - Tallinn University of Technology - engineer
2000 – 2003 - Tallinn University of Technology - scientific projects at TUT
8.Academic degree Master of Science
9.Dates and sites of
earning the degrees
Tallinn University of Technology, 2001
10.Honours/awards 2004, EITSA Scholarship for PhD students in ICT field
2005, EITSA Scholarship for PhD students in ICT field
11.Research-administrative
experience
12.Supervised dissertations
13.Current research program Fault simulation methods for digital systems
14.Current grant funding 5637, High-Level Test Generation and Testability Analysis for Digital Circuits, J. Raik
15.List of most important publications

R. Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE International Semiconductor Conference, CAS’2004, Vol. 2, pp. 459-462, Sinaia, Romania, Oct. 4-6, 2004.

R.Ubar, M.Aarna, M.Brik, J.Raik. High-Level Fault Modeling in Digital Systems. Synergies between Information Processing and Automation, International Conference IWK, Shaker Verlag, Vol.2, pp. 486-491, Ilmenau, Germany, September 27-30, 2004.

R.Ubar, M.Aarna, M.Brik, T.Evartson, J.Raik. High Level Fault Models for Digital Systems. In "University Research, Industry, International Cooperation", Minsk, 2004 pp.303-310.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester - Diagnostic Package for Research and Training. J. of Radioelectronics and Informatics, No3 (24), July - September, 2003, pp. 69-73.

M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits, Proc. of 42th International Scientific Conference of Riga Technical University, pp.91-94, Riga, October 11-13, 2001.

last updated: 03.08.2005

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