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| Elulookirjeldus (CV) | ||
| 1. | Eesnimi | Eero |
| 2. | Perekonnanimi | Ivask |
| 3. | Töökoht | Tallinna Tehnikaülikool |
| 4. | Ametikoht | Teadur |
| 5. | Sünniaeg | 03.09.1971 (päev.kuu.aasta) |
| 6. | Haridus | 1998 astumine TTÜ doktoriõppesse 1998- Tallinna Tehnikaülikool Tehn. tead. magister 1996- Tallinna Tehnikaülikool, Inseneri diplom 1989- Tallinna 46. Keskkooli lõpetamine |
| 7. | Teenistuskäik | 2005 - Uurimistöö Fraunhoferi Instituut, Dresden, Saksamaa (2 nädalat) 2003 – Uurimistöö Fraunhoferi Instituut, Dresden, Saksamaa (1 kuu) 2001 - “Tulemüüri kasutamine süsteemiga MOSCITO” Fraunhoferi Instituut, Dresden, Saksamaa (1 kuu) 2000 - “Internetipõhine testigenererimine süsteemiga MOSCITO” Fraunhoferi Instituut, Dresden, Saksamaa (1 kuu) 1999 - teadustöö teemal "Disain ja testimine" Fraunhoferi Integraalskeemide Instituudis Dresdenis, Saksamaal (1 kuu) 1998- uurimistöö teemal "Disain ja testimine" Fraunhoferi Integraalskeemide Instituudis Dresdenis, Saksamaal (1 kuu) Teadustöö Tallinna Tehnikaülikoolis: ETF G1850 (1996-1999) Hierarhilised testigenereerimise meetodidINCO 977133 - VILABETF G574 (1993-1995), ETF G1880 (1996-1998) 1999 (15.01-15.04) uurimistöö Rootsi Kuninglikus Tehnoloogia-instituudis (ESD labor) VISBY projekti raames teemal: "Multiparadigmaline tarkvara/riistvara arenduskeskond IRSYD "Teadustöö Tallinna Tehnikaülikoolis: ETF G574 (1993-1995), ETF G1880 (1996-1998) 1996- uurimisprojekt "Mittetäielikud teadmised" Tehisintellekti labor,Savoie Instituut Prantsusmaa (7 kuud) 1995- uurimistöö teemal "Disain ja Testimine" TIMA laboris Grenoble Polütehniline Instituut, Prantsusmaa (3 kuud) |
| 8. | Teaduskraad | Tehnikateaduste Magister |
| 9. | Teaduskraadi välja andnud asutus, aasta |
1998 a., Tallinna Tehnikaülikool |
| 10. | Tunnustused | 1997- Esimene auhind Eesti Kultuuriministeeriumi ja ETF-i tudengitööde riiklikul konkursil tehnika valdkonnas (kollektiivne töö: teaduspublikatsioonid 1996-1997) |
| 11. | Teadusorganisatsiooniline ja –administratiivne tegevus |
|
| 12. | Juhendamisel kaitstud väitekirjad |
|
| 13. | Teadustöö põhisuunad | Digitaalse riistvara disain ja testimine: geneetilised algoritmidInternetipõhine testigenereerimine, rikete simuleerimineRiistvara kirjeldamise keele VHDL transleerimine |
| 14. | Jooksvad grandid | Sihtfinantseerimise teema: 0142508s03" Digitaalsüsteemide disain ja test” Digitaalskeemide defekt-orienteeritud diagnostika (G-5649). Eesti Teadusfondi grant, (2003-2006). Isetestivad digitaalsüsteemid (G-5910). Eesti Teadusfondi grant, 2004-2007 Framework V Project IST - 2001 - 37592 "Establishment of the Virtual Centre of Excellence for IST RTD in Estonia - EVIKINGS" (2002-2005) V Framework IST-2001-37592 (2002-2005) “eVIKINGS II” – Establishment of the Virtual Centre of Excellence for Information Society Technologies RTD in Estonia |
| 15. | Teaduspublikatsioonid |
Brik, M., Ivask, E., Raik, J., Ubar, R. On Using Genetic Algorithm for Test Generation. Proc. 9th Biennial Baltic Electronics Conference, Tallinn, Estonia, 2004, p.233-236 Brik, M., Raik, J., Ubar, R., Ivask, E. GA-based Test Generation for Sequential Circuits. 2nd East-West Design & Test Workshop EWDTW-2004,, Alushta, Ukraina, 2004, p.30-34 E. Ivask, J. Raik, R. Ubar Web-based environment for digital electronics test tools. IFIP PRO-VE (Virtual Enterprises and Collaborative Networks 2004), Toulouse 2004 E. Ivask, P. Ellervee VHDL Front-End for High-Level Synthesis Tool xTractor. Baltic Electronic Conference 2004, Tallinn Ivask, E., Jutman, A., Orasson, E., Raik, J., Ubar, R., H-D.Wuttke. Research Environment for Teaching Digital Test. 49. Int. Conf. IWK, Ilmenau, Germany, 2004, p.468-473 M. Brik, J. Raik, R. Ubar, E. Ivask On Using Genetic Algorithm for Test Generation Baltic Electronic Conference 2004, Tallinn Aarna, M., Ivask, E., Jutman, A., Orasson, E., Raik, J., Ubar, R., Vislogubov, V., Wuttke, H.D. Turbo Tester - Diagnostic Package for Research and Training.. The 1st East-West Design and Test Conference, Alushta, 2003 Schneider, A., Diener, K.-H., Elst, G., Ubar, R., Ivask, E., Raik, J. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO.. Proc. of 7th World Multiconference on Systemics, Cybernetics and Informatics - SCI 2003., Orlando, USA, 2003, p.136-141 André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng: Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD 2002: 187-195 A.Schneider, E.Ivask, P.Miklos, J.Raik, K.H.Diener, R.Ubar,T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of Design Automation and Test in Europe - DATE'02. Paris, March 4-8, 2002, pp. 221-226 R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. IEEE Workshop on Electronic Design,Test and Applications - DELTA'02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91 Schneider,A., Diener,K.-H., Elst,G., Ivask,E., Raik,J., Ubar,R. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proc. IFIP Conference on IP Based SOC Design, Grenoble, France, 2002, p.357-362 Schneider,A., Diener,K.-H., Ivask,E., Ubar,R., Gramatova,E., Fisherova,M., Pleskacz,W., Kuzmicz,W. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, 2002, p.303-306 Schneider,A., Diener,K.-H., Ivask,E., Ubar,R., Gramatova,G., Hollstein,T., Pleskacz,W., Kuzmicz,W., Peng,Z. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. EUROMICRO Conference, 2002, p.187-194 Ubar,R., Raik,J., Ivask,E., Brik,M. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis) Ser.: Elec. Energ, 2002, Vol.15, No.1, p.123-1 Ubar,R., Raik,J., Ivask,E., Brik,M. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, 2002, p.315-319 Diener, K.-H., Elst, G., Ivask, E., Jervan, G., Peng, Z., Raik, J., Ubar. R. Digital Design Flow with Test Activities. VILAB User Forum, Smolenice, 2000, 11 p. E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Design and Diagnostics of Electronic Circuits and Systems - DDECS'2001, Györ, Hungary, April 18-20, 2001, pp.57-60 R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics. Nis,Yugoslavia, May 12-15 2001, Vol.2, pp.617-620 Schneider,A., Ivask,E., Raik,J., Miklos,P., Diener,K.H., Ubar,R., Kuzmicz,W., Pleskacz,W., Gramatova,E. VILAB Test Generation Tools Running Under the MOSCITO System. VILAB User Forum, Györ, Hungary, 2001, 12p. Schneider,A., Schneider,P., Gramatova,E., Ivask,E. Internet-basierter Systementwurf mit MOSCITO. In "Entwurf Integrierter Schaltungen" 10. E.I.S. Workshop, Dresden, 2001, p.295-296 Ubar,R., Raik,J., Ivask,E., Brik,M. Hierarchical Fault Simulation in Digital Systems. Proceedings of Int. Symp. on Signals, Circuits and Systems SCS'2001, Iasi, Romania, 2001, p.181-184 Ivask, E., Ellervee, P. Mapping of VHDL Structures for Generic EDA Database Format IRSYD. Proceedings of the 7th Biennial Baltic Electronic Conference (BEC'2000), Tallinn, 2000, p.317-320 Ivask, E., Raik, J., Ubar, R. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. 7th Baltic Electronics Conference, Tallinn, 2000, p.129-132 Ivask, E., Ubar, R., Raik, J. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, Cascais, Portugal, 2000, p.319-320 Elst,G., Diener,K-H., Ivask,E, Raik,J., Ubar,R. FPGA Design Flow with Automated Test Generation. Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems, Potsdam, 1999, p.120-123 E.Ivask, Raik,J., Ubar,R. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the 6th Baltic Electronics Conference, Tallinn, 1998, p.163-166 |
viimati muudetud: 03.08.2005
| Curriculum Vitae (CV) | ||
| 1. | First Name | Eero |
| 2. | Surname | Ivask |
| 3. | Institution | Tallinn University of Technology |
| 4. | Position | Reseacher |
| 5. | Date of birth | 03.09.1971 (day.month.year) |
| 6. | Education | 1998 - Tallinn Technical University, Ph.D Student 1998 – Tallinn Technical University, Master of Science 1996 - Tallinn Technical University, Diploma of Eng. 1989 – graduation of Tallinn 46. Highschool |
| 7. | Research and professional experience |
2005 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 2 weeks 2003 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 1 month 2001 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 1 month 2000 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 1 month (Internet based test generation and fault simulation) 1999 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 1 month 1999 15.01-15.04 Research in ESD Lab in Royal Institute of Technology in Sweden in frame of VISBY project 1998 Research Fraunhofer Gesellschaft, Institute of Integrated Circuits, Dresden, 1 month 1996 Research project “Incomplete knowledge”, Laboratory of Artificial Inteligence, Chambery Uinversity in France, 7 months1995 Research project in TIMA laboratory in Grenoble Polytechnical University in France, 3 months 1995 Research project "Design and Test" TIMA laboratory Grenoble Polytechnical Instituut, France (3 kuud) |
| 8. | Academic degree | Master of Science |
| 9. | Dates and sites of earning the degrees |
1998 Tallinn University of Technology |
| 10. | Honours/awards | 1997- First prize in student work contest arranged by Estonian Cultural minirtry and Estonian Science Foundation in technical subject (Scientific publications 1996 – 1997) |
| 11. | Research-administrative experience |
|
| 12. | Supervised dissertations | |
| 13. | Current research program | Design and test of digital systems. Genetic algorithms, intenet based test generation, fault simulation. Translation of hardware description language VHDL |
| 14. | Current grant funding | Framework V Project IST - 2001 - 37592 "Establishment of the Virtual Centre of Excellence for IST RTD in Estonia - EVIKINGS" (2002-2005) V Framework IST-2001-37592 (2002-2005) “eVIKINGS II” – Establishment of the Virtual Centre of Excellence for Information Society Technologies RTD in Estonia |
| 15. | List of most important publications |
Brik, M., Ivask, E., Raik, J., Ubar, R. On Using Genetic Algorithm for Test Generation. Proc. 9th Biennial Baltic Electronics Conference, Tallinn, Estonia, 2004, p.233-236 Brik, M., Raik, J., Ubar, R., Ivask, E. GA-based Test Generation for Sequential Circuits. 2nd East-West Design & Test Workshop EWDTW-2004,, Alushta, Ukraina, 2004, p.30-34 E. Ivask, J. Raik, R. Ubar Web-based environment for digital electronics test tools. IFIP PRO-VE (Virtual Enterprises and Collaborative Networks 2004), Toulouse 2004 E. Ivask, P. Ellervee VHDL Front-End for High-Level Synthesis Tool xTractor. Baltic Electronic Conference 2004, Tallinn Ivask, E., Jutman, A., Orasson, E., Raik, J., Ubar, R., H-D.Wuttke. Research Environment for Teaching Digital Test. 49. Int. Conf. IWK, Ilmenau, Germany, 2004, p.468-473 M. Brik, J. Raik, R. Ubar, E. Ivask On Using Genetic Algorithm for Test Generation Baltic Electronic Conference 2004, Tallinn Aarna, M., Ivask, E., Jutman, A., Orasson, E., Raik, J., Ubar, R., Vislogubov, V., Wuttke, H.D. Turbo Tester - Diagnostic Package for Research and Training.. The 1st East-West Design and Test Conference, Alushta, 2003 Schneider, A., Diener, K.-H., Elst, G., Ubar, R., Ivask, E., Raik, J. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO.. Proc. of 7th World Multiconference on Systemics, Cybernetics and Informatics - SCI 2003., Orlando, USA, 2003, p.136-141 André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng: Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD 2002: 187-195 A.Schneider, E.Ivask, P.Miklos, J.Raik, K.H.Diener, R.Ubar,T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of Design Automation and Test in Europe - DATE'02. Paris, March 4-8, 2002, pp. 221-226 R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. IEEE Workshop on Electronic Design,Test and Applications - DELTA'02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91 Schneider,A., Diener,K.-H., Elst,G., Ivask,E., Raik,J., Ubar,R. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proc. IFIP Conference on IP Based SOC Design, Grenoble, France, 2002, p.357-362 Schneider,A., Diener,K.-H., Ivask,E., Ubar,R., Gramatova,E., Fisherova,M., Pleskacz,W., Kuzmicz,W. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, 2002, p.303-306 Schneider,A., Diener,K.-H., Ivask,E., Ubar,R., Gramatova,G., Hollstein,T., Pleskacz,W., Kuzmicz,W., Peng,Z. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. EUROMICRO Conference, 2002, p.187-194 Ubar,R., Raik,J., Ivask,E., Brik,M. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis) Ser.: Elec. Energ, 2002, Vol.15, No.1, p.123-1 Ubar,R., Raik,J., Ivask,E., Brik,M. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, 2002, p.315-319 Diener, K.-H., Elst, G., Ivask, E., Jervan, G., Peng, Z., Raik, J., Ubar. R. Digital Design Flow with Test Activities. VILAB User Forum, Smolenice, 2000, 11 p. E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Design and Diagnostics of Electronic Circuits and Systems - DDECS'2001, Györ, Hungary, April 18-20, 2001, pp.57-60 R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics. Nis,Yugoslavia, May 12-15 2001, Vol.2, pp.617-620 Schneider,A., Ivask,E., Raik,J., Miklos,P., Diener,K.H., Ubar,R., Kuzmicz,W., Pleskacz,W., Gramatova,E. VILAB Test Generation Tools Running Under the MOSCITO System. VILAB User Forum, Györ, Hungary, 2001, 12p. Schneider,A., Schneider,P., Gramatova,E., Ivask,E. Internet-basierter Systementwurf mit MOSCITO. In "Entwurf Integrierter Schaltungen" 10. E.I.S. Workshop, Dresden, 2001, p.295-296 Ubar,R., Raik,J., Ivask,E., Brik,M. Hierarchical Fault Simulation in Digital Systems. Proceedings of Int. Symp. on Signals, Circuits and Systems SCS'2001, Iasi, Romania, 2001, p.181-184 Ivask, E., Ellervee, P. Mapping of VHDL Structures for Generic EDA Database Format IRSYD. Proceedings of the 7th Biennial Baltic Electronic Conference (BEC'2000), Tallinn, 2000, p.317-320 Ivask, E., Raik, J., Ubar, R. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. 7th Baltic Electronics Conference, Tallinn, 2000, p.129-132 Ivask, E., Ubar, R., Raik, J. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, Cascais, Portugal, 2000, p.319-320 Elst,G., Diener,K-H., Ivask,E, Raik,J., Ubar,R. FPGA Design Flow with Automated Test Generation. Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems, Potsdam, 1999, p.120-123 E.Ivask, Raik,J., Ubar,R. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the 6th Baltic Electronics Conference, Tallinn, 1998, p.163-166 |
last updated: 03.08.2005
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