[ sulge aken ]
| Elulookirjeldus (CV) | ||
| 1. | Eesnimi | Tatjana |
| 2. | Perekonnanimi | Shchenova (Vassiljeva) |
| 3. | Töökoht | Tallinna Tehnikaülikool, Arvutitehnika instituut |
| 4. | Ametikoht | Erakorraline teadur |
| 5. | Sünniaeg | 30.05.1979 (päev.kuu.aasta) |
| 6. | Haridus | 2005 - ... Tallinna Tehnikaülikool - doktoriõpe 2003 - 2005 Tallinna Tehnikaülikool - magistriõpe - eriala: arvuti- ja süsteemitehnika 1999 - 2003 Tallina Tehnikaulikool - bakalaureuseõpe - eriala: arvuti- ja süsteemitehnika Täiendkoolitus: 2005 - ARTIST2 Summer School on Component & Modelling, Testing & Verification, and Statical Analysis of Embedded Systems (Nässlingen, Rootsi) - 1 nädal 2004 - Linköpingi Ülikool, Rootsi: külalistudeng (3 kuu) 2003 - Ilmenau Tehnikaülikool, Saksamaa: külalistudeng (1 kuu) Kutseharidus: 1997 - 1999 Narva Kutseõppekeskus - eriala: arvuti- ja süsteemitehnika Keskharidus: 1997 Narva linna Kreenholmi Gümnaasium |
| 7. | Teenistuskäik | 2005 - Tallinna Tehnikaülikooli teadur |
| 8. | Teaduskraad | Tehnikateaduste magistri kraad Tehnikateaduste bakalaureuse kraad |
| 9. | Teaduskraadi välja andnud asutus, aasta |
Tallina Tehnikaülikool, 2005 Tallina Tehnikaülikool, 2003 |
| 10. | Tunnustused | |
| 11. | Teadusorganisatsiooniline ja –administratiivne tegevus |
|
| 12. | Juhendamisel kaitstud väitekirjad |
|
| 13. | Teadustöö põhisuunad | Digitaalskeemide simuleerimine ja verifitseerimine Binaarsed otsustusdiagrammid Digitaalsüsteemide isetestimine Testprogrammide koostamine ja optimeerimine |
| 14. | Jooksvad grandid | |
| 15. | Teaduspublikatsioonid |
G.Jervan, Z.Peng, R.Ubar, T.Shchenova. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, 2005, (accepted for publication) Ubar, R., Shchenova, T., Jervan, G., Zebo, P. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. The 10th European Test Symposium, Tallinn, Estonia, May 2005, p.2-7 Ubar, R., Vassiljeva, T., Raik, J., Jutman, A., Tombak, M., Peder, A. Optimization of Structurally Synthesized BDDs. The 4th IASTED International Conference on Modelling, Simulation and Optimization, Kauai, Hawaii, USA, 2004, p.234-240 |
viimati muudetud: 25.01.2006
| Curriculum Vitae (CV) | ||
| 1. | First Name | Tatjana |
| 2. | Surname | Shchenova (Vassiljeva) |
| 3. | Institution | Tallinn University of Technology, Department of Computer Engineering |
| 4. | Position | Extraordinary research fellow |
| 5. | Date of birth | 30.05.1979 (day.month.year) |
| 6. | Education | 2005 - ... Tallinn University of Technology - Graduate studies - Information and Communication Technology 2003 - 2005 Tallinn University of Technology - Master studies - Computer and Systems Engineering 1999 - 2003 Tallinn University of Technology - Bachelor studies - Computer and Systems Engineering Additional studies: 2005 - ARTIST2 Summer School on Component & Modelling, Testing & Verification, and Statical Analysis of Embedded Systems (Nässlingen, Sweden) - 1 week 2004 - Linköping University, Sweden: guest student (3 months) 2003 - Ilmenau Technical University, Germany: guest student (1 months) Vocational education: 1997 - 1999 Narva Vocation Training Centre - Computer and Systems Engineering Secondary education: 1997 Narva Kreenholm Gymnasium |
| 7. | Research and professional experience |
2005 - Tallinn University of Technology, research fellow |
| 8. | Academic degree | M.Sc. B.Sc. |
| 9. | Dates and sites of earning the degrees |
Tallinn University of Technology, 2005 Tallinn University of Technology, 2003 |
| 10. | Honours/awards | |
| 11. | Research-administrative experience |
|
| 12. | Supervised dissertations | |
| 13. | Current research program | Fault modelling Binary decision diagrams Embedded self-test Test set optimization |
| 14. | Current grant funding | |
| 15. | List of most important publications |
G.Jervan, Z.Peng, R.Ubar, T.Shchenova. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, 2005, (accepted for publication) Ubar, R., Shchenova, T., Jervan, G., Zebo, P. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. The 10th European Test Symposium, Tallinn, Estonia, May 2005, p.2-7 Ubar, R., Vassiljeva, T., Raik, J., Jutman, A., Tombak, M., Peder, A. Optimization of Structurally Synthesized BDDs. The 4th IASTED International Conference on Modelling, Simulation and Optimization, Kauai, Hawaii, USA, 2004, p.234-240 |
last updated: 25.01.2006
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