Artjom Kurbatov, MSc, 2005, juh. Raimund Ubar. SSBDD mudeli omaduste uurimine testi gen. aja vähendamiseks. TTÜ

Joachim Sudbrock, MSc, 2005, juh. Raimund Ubar. Defect-oriented ATPG for standard cell ASIC designs. TTÜ

Tatjana Shchenova, MSc, 2005, juh. Raimund Ubar. Energy minimization in HBIST for SOC. TTÜ

Artur Jutman, PhD, 2004, juh. Raimund Ubar. Selected issues of modeling, verification and testing of digit. Systems. TTÜ

Dmitri Zhukov, MSc, 2004, juh. Raimund Ubar, Artur Jutman. Development of an educational environment based on DEFSIM. TTÜ

Jekaterina Grüning, MSc, 2004, juh. Raimund Ubar. Õppevah. aines “Digit.süst. diagnostika”. Diagnostiline modelleerimine. TTÜ

Jelena Tünni, MSc, 2004, juh. Raimund Ubar. Õppevahend aines “Digit.süst. diagnostika”.Rikete süntees ja analüüs. TTÜ

Julia Smahtina, MSc, 2004, juh. Raimund Ubar. Hybrid Functional BIST. TTÜ

Maksim Jenihhin, MSc, 2004, juh. Raimund Ubar. Test Time Minimization for Parellel Hybrid BIST Architectures. TTÜ

Natalja Mazurova, MSc, 2004, juh. Raimund Ubar. Functional BIST with DFT. TTÜ

Vineeth Govind, MSc, 2004, juh. Raimund Ubar, Jaan Raik. RTL Test Point Insertion for Improving Testability in Sequential Circuits. TTÜ

Vladisl. Vislogubov, MSc, 2004, juh. Raimund Ubar. Webipõhise õppesüsteemi väljatöötamine aines Digitaalsüsteemide diagnostika. TTÜ

Elmet Orasson, MSc, 2003, juh. Raimund Ubar. Digitaalsüsteemide testi- ja diagnostika-alase õppetarkvara arendus. TTÜ

Helena Kruus, MSc, 2003, juh. Raimund Ubar. Iteratiivsed mittedeterministlikud optimeerimisalgoritmid. TTÜ

Marina Brik, PhD, 2002, juh. Raimund Ubar. Investigation and Development of Test Generation Methods for Control Part of Digital Systems. TTÜ

Rein Raidma, MSc, 2002, juh. Raimund Ubar, Jaan Raik. Kontrollitavuse parandamisel põhinev järjestikskeemide isetestimise meetod. TTÜ

Jaan Raik, PhD, 2001, juh. Raimund Ubar. Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams. TTÜ

Jaanus Heinlaid, MSc, 2001, juh. Raimund Ubar. Digitaalskeemide signaalijälgitavuste analüüs ja arvutamine. TTÜ

Lennart Raun, MSc, 2001, juh. Raimund Ubar. Digitaalskeemide signaalijuhitavuste analüüs ja arvutamine. TTÜ

Margit Aarna, MSc, 2001, juh. Raimund Ubar. Digitaalskeemide rikete paraleelne simuleerimine binaarsetel otsustusdiagrammidel. TTÜ

Artur Jutman, MSc, 1999, juh. Raimund Ubar. Design Error Diagnosis in Digital Circuits. TTÜ

Julia Dushina, PhD, 1999, juh. Dominique Borionne, Raimund Ubar. Verification formelle des resultats de la Synthese de Haut Niveau. Grenoble’i Fourier’ Ülikool

Eero Ivask, MSc, 1998, juh. Raimund Ubar. Genetic Algorithms in Test Pattern Generation. TTÜ

Gert Jervan, MSc, 1998, juh. Raimund Ubar. Decision Diagram Synthesis from VHDL. TTÜ

Priidu Paomets, MSc, 1998, juh. Raimund Ubar. An Open and Dynamic User Interface to the CAD system Turbo-Tester. TTÜ

Jaan Raik, MSc, 1997, juh. Raimund Ubar. Alternatiivsetel graafidel põhinev hierarhiline testide generaator. TTÜ

Viktor Zaugarov, MSc, 1994, juh. Raimund Ubar. Testide genereerimine mikroprotsessoritele. TTÜ

Ahto Buldas, MSc, 1993, juh. Raimund Ubar. Digitaalskeemide simuleerimise algebraliste meetodite analüüs. TTÜ

Helena Krupnova, MSc, 1993, juh. Raimund Ubar. Constraints Analysis in Hierarchical Test Generation for Digital Systems. TTÜ

Julia Dushina, MSc, 1993, juh. Raimund Ubar. Test Generation for Data Paths of Digital Systems. TTÜ

Marina Brik, MSc, 1993, juh. Raimund Ubar. Test Synthesis for Finite State Machines. TTÜ

Teet Evartson, cand, 1987, juh. Raimund Ubar. Issledovanije i razrabotka metodov poiska neispravnostei v tsifrovyh shemah. Küberneetika instituut

Andrus Voolaine, MSc, 1986, juh. Raimund Ubar. Issledovanije i razrabotka metodov mnogoznatshnogo modelirovanija neispravnostei tsivrovyh shem. Küberneetika instituut

Martin Pall, cand, 1986, juh. Raimund Ubar. Issledovanije i razrabotka metodov generirovanija testov dlja tsifrovyh shem. Küberneetika instituut

Mari Plakk, cand, 1984, juh. Raimund Ubar. Razrabotka i issledovanije metodov sinteza testov dlja dickretnyh ustroistv na osnove modeli alternativnyh grafov. küberneetika instituut

Peeter Kitsnik, cand, 1981, juh. Raimund Ubar. Issledovanije i razrabotka metodov analiza diagnostitsheskih testov dlja tsifrovyh shem. Küberneetika instituut

A.Jutman, J.Raik, R.Ubar. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419

A.Jutman, R.Ubar, J.Raik. Generic Interconnect BIST for Network-on-Chip. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron, April 13-16, 2005, pp.224-227

A.Jutman, R.Ubar, J.Raik. New Built-In Self-Test Scheme for SoC Interconnect. Proceedings of the 9th World Multi-Conference on Systemics, Cybernetics and Informatics. July 10-13, 2005, Orlando, Florida, USA, vol.4, pp.19-24.

A.Jutman, V.Rosin, A.Sudnitson, R.Ubar, H.-D.Wuttke A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. Proceedings of EAEEIE, June 2005. Best Paper Award.

A.Matrosova, A.Pleshkov, R.Ubar. Construction of the Tests of Combinational Circuit Failures by Analyzing the Orthogonal Disjunctive Normal Forms Represented by the Alternative Graphs. J. of Automation and Remote Control. Publisher: Springer Science & Business Media B.V., 66 (2), 2005, pp. 313-327.

A.Matrosova, A.Pleshkov, R.Ubar. Test Generation for Combinational Circuits by Orthogonal Disjunctive Normal Forms and SSBDDs. Avtomatika i Telemekhanika, No. 2, 2005, pp. 158–174 (in Russian).

E.Gramatova, M.Fisherova, R.Ubar, W.Pleskacz. Chapter 2. Defects, Faults and Fault Models. In “Handbook of Electronic Testing”. Czech TU Publishing House, Prague, 2005, pp. 26-98.

G.Jervan, R.Ubar, Z.Peng, P.Eles. Chapter 5. Test Generation: A Hierarchical Approach. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 63-77

G.Jervan, R.Ubar, Z.Peng, P.Eles. Chapter 7. An Approach to System Level DFT. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 91-118

G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Technique for Hybrid BIST Test Set Generation. Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems - DDECS Workshop. Sopron, April 13-16, 2005, pp.182-185.

G.Jervan, Z.Peng, R.Ubar, T.Shchenova. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, 2005, pp.1-20 (accepted).

IEEE 10th European Test Symposium. Informal Digest of Papers. Editors: R.Ubar, P.Prinetto, B.Al-Hashimi, M.Renovell, P.Muhmenthaler, Ch. Landrault. Tallinn, Estonia, May 22-25, 2005, 286 p.

IEEE Proceedings of the 10th European Test Symposium. Editors: R.Ubar, P.Prinetto, M.Renovell, P.Muhmenthaler, Ch. Landrault. Tallinn, Estonia, May 22-25, 2005, 230 p.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. IEEE Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.72-78.

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. IEEE Proceedings of the 6th Latin-American Test Workshop – LATW2005, March 30 – April 2, 2005, Salvador, Bahia, Brazil, pp.325-330

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.96-101

J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York 2005, pp. 332-344

J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications – JETTA. Springer Science + Business Media, Inc. 21, pp.73-84, 2005

J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

M.Balas, M.Fisherova, E.Gramatova, A.Jutman, Z.Kotasek, O.Novak, T.Pikula, J.Raik, J.Strnadel, R.Ubar, J.Zahradka. Testing Tools for Training and Education. Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.671-676.

M.Brik, E.Fomina, R.Ubar. A Proposal for Optimisation of Low-Powered FSM Testing. 3rd East-West Design & Test Workshop EWDTW-2005, Odessa, Sept. 15-18, 2005, pp.15-20.

O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p.

O.Novak, E.Gramatova, R.Ubar. IST Project REASON – Handbook of Testing Electronic Systems. IEEE Proceedings of the 5th European Dependable Computing Conf. – EDCC-5, Budapest, April 20-22, 2005, pp.15-18.

R.Ubar. Digitaalsüsteemide diagnostika. I. Diagnostiline modelleerimine. Tallinn, TTÜ Kirjastus, 2005, 148 lk.

R.Ubar, E.Gramatova, M.Fisherova. Chapter 3. Test Generation Techniques and Algorithms. In “Handbook of Electronic Testing”. Czech TU Publishing House, Prague, 2005, pp. 100-174.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Teaching Advanced Test Issues in Digital Electronics. Proceedings of the 6th IEEE International Conference on Information Technology Based Higher Education and Training - ITHET. July 7-9, 2005, Santo Domingo, pp. S2B-5 – S2B-10.

R.Ubar, H.-D.Wuttke. Research and Training Environment for Digital Design and Test. Proc. of the 8th IASTED Int. Conf. on Computers and Advanced Technology in Education. Oranjestadt, Aruba, August 29-31, 2005, pp.232-237.

R.Ubar, P.Prinetto, J.Raik. 10th IEEE European Test Symposion. IEEE Journal of Design & Test of Computers, Sept. - Oct., 2005.

R.Ubar, T.Shchenova, G.Jervan, Z.Peng. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. IEEE Proceedings of the 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.2-7.

T.Bengtsson, A.Jutman, R.Ubar, S.Kumar. A method for crosstalk fault detection in on-chip Buses. IEEE NORCHIP Conference, Oulu, Finland, Nov. 21-22, 2005.

T.Bengtsson, A.Jutman, S.Kumar, R.Ubar. Delay Testing of Asynchronous NOC Interconnects. Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.419-424.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar, J.Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Digest of Papers of the 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.151-155

A.Jutman, A.Peder, J.Raik, M.Tombak, R.Ubar. Structurally Synthesized Binary Decision Diagrams. Proc. of the 6th International Workshop on Boolean Problems, Freiberg, Germany, Sept. 2004, pp.271-278

A.Jutman, A.Sudnitson, R.Ubar, and H.-D.Wuttke, "Asynchronous E-Leaning Resources for Hardware Design Issues", in Proc. International Conference on Computer Systems and Technologies (CompSysTech'2004), Sofia, Bulgaria, 2004, v. IV, pp. 11.1-11.6. (ISBN: 954-9641-38-4).

A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. E-Learning Environment in the Area of Digital Microelectronics. IEEE Proceedings of the 5th Int. Conf. on Information Technology Based Higher Education and Training - ITHET 2004, Istambul, Turkey, 31 May – 2 June 2004, pp.278-283

A.Jutman, E.Gramatova, T.Pikula, R.Ubar. E-Learning Tools for Teaching Self-Test of Digital Electronics. 15 EAEEIE International Conf. on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, May 27-29, 2004, pp. 267-272.

A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. 5th European Workshop on Microelectronics Education – EWME 2004, Lausanne, April 15-16, 2004, pp. 173-176.

A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. In “Microelectronics Education” Kluwer Academic Publishers, 2004, pp.253-258.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment for Teaching Digital Test. Proceedings of the 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473

E. Ivask, J. Raik, R. Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer Academic Publishers, 2004, pp. 435-442.

G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Methodology for Hybrid BIST Cost Calculation. IEEE Proceedings of the 22nd Norchip Conference, Oslo, November 8-9, 2004, pp.297-300.

J.Raik, A.Krivenko, R.Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.225-228.

J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST with Status BIT Control. Proceedings of the Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.507-510.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. 2nd IEEE East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.35-40.

J.Raik, R.Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. IEEE Proceedings of the 7th Workshop on Design and Diagnostics of Electronic Circuits and Systems – DDECS 2004. Stara Lesna, Slovakia, April 18-21, 2004, pp. 219-222.

J.Raik, R.Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. IEEE Proceedings of the 9th European Test Symposium, Ajaccio, Corsica, France, May 23-26, 2004, pp. 17-18.

J.Raik, V.Govind, R.Ubar. RT-Level Test Point Insertion for Sequential Circuits. Proc. of the IEEE 1st International Workshop on Testability Assessment – IWoTA-2004, Rennes, Nov.2, 2004, pp.34-40. IEEE Catalog Number 04EX983, ISBN 0-7803-8851-8.

M.Brik, E.Ivask, J.Raik, R.Ubar. On Using Genetic Algorithm for Test Generation. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.233-236.

M.Brik, J.Raik, R.Ubar, E.Ivask. GA-based Test Generation for Sequential Circuits. 2nd IEEE East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.30-34.

N.Mazurova, J.Smahtina, R.Ubar. Hybrid Functional BIST for Digital Systems. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.205-208.

P.Ellervee, J.Raik, V.Tihhomirov, R.Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the 22nd IEEE Norchip Conference, Oslo, November 8-9, 2004, pp.59-62.

R.Ubar. Diagnostic Modelling of Digital Systems with Decision Diagrams. Proceedings of Tomsk State University, No 9 (I), August 2004, pp.174-179.

R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test. Frontiers in Education Conference – FIE, Savannah, USA, October 20-23, 2004.

R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test. Proceedings of the 34th ASEE/IEEE Frontiers in Education Conference, October 20-23, 2004, Savannah, GA, pp.S3F-18 to S3F-24. IEEE Catalog Number: 04CH37579. ISBN: 0-7803-8552-7. Library of Congress: 79-640910. ISSN: 0190-5848.

R.Ubar, H.-D.Wuttke. Research and Training Scenarios for Design and Test of SOC. Proc. of the World Congress on Engineering and technology Education. March 14-17, 2004, Guaruja/Santos, Brasil, pp.320-324

R.Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE Proceedings of the International Semiconductor Conference, CAS’2004, Sinaia, Romania, Oct. 4-6, 2004, pp.459-462.

R.Ubar, M.Aarna, M.Brik, J.Raik. High_Level Fault Modeling in Digital Systems. 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.486-491.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. IEEE Proceedings of the 5th Latin-American Test Workshop – LATW 2004. Cartagena, Colombia, March 8-10, 2004, pp.98-103.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architectures. System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Hybrid BIST Optimization for Core-Based Systems with Test Pattern Broadcasting. IEEE Proceedings of the 2nd Int. Workshop on Electronic Design, Test and Applications – DELTA’04, Perth, Australia, 28-30 January 2004, pp.3-8.

R.Ubar, N.Mazurova, J.Smahtina, E.Orasson, J.Raik. HyFBIST: Hybrid Functional Built-In Self-Test in Microprogrammed Data-Paths of Digital Systems. Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.497-502.

R.Ubar, T.Vassiljeva, J.Raik, A.Jutman, M.Tombak, A.Peder. Optimization of Structurally Synthesized BDDs. Proceedings of the 4th IASTED International Conference on Modelling, Simulation and Optimization, Kauai, Hawaii, USA, August 17-19, 2004, pp.234-240.

V.Hahanov, R.Ubar. 2nd IEEE EastWest Design & Test Workshop. IEEE Journal of Design & Test of Computers, Nov.-Dec 2004, pp.594.

V.Vislogubov, A.Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.255-258.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar. Evolutionary approach to the functional test generation for digital circuits. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.229-232.

A. Jutman, A. Sudnitson, R. Ubar. Digital Design Learning System Based on Java Applets. The 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, 2003, pp.183-187.

A. Jutman, A. Sudnitson, R. Ubar. Web-Based Training System for Teaching Principles of Boundary Scan Technique. EAEEIE International Conference, Lodz, Poland, 16-18 June 2003.

A.Jutman, A.Sudnitsõn, R.Ubar, D.Wuttke. Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test. Proceedings of the 4th Int. Conf. on Information Technology Based Higher Education and Training - ITHET. Marrakech, Morocco, July 7-9, 2003, pp.397-401

A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. Proc. of 7th World Multiconference on Systemics, Cybernetics and Informatics – SCI 2003. Orlando, USA, July 27-30, 2003, pp.136-141.

G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. IEEE Proceedings of the 18th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003, pp.225-232.

G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. IEEE Proceedings of the 12th Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003, pp. 318-323

J.Raik, R.Raidma, R.Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. IEEE Proceedings of the 21st Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.220-223.

J.Raik, R.Ubar. DECIDER: A System for Hierarchical Test Pattern Generation. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 40-45.

J.Raik, T.Nõmmeots, R.Ubar. New Method of Testability Calculation to Guide RT-Level Test Generation. IEEE Proceedings of 4th Latin-American Test Workshop – LATW2003, Natal, Brazil, February 16-19, 2003, pp.46-51.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester – Diagnostic Package for Research and Training. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 69-73.

R.Ubar. Decision Diagrams and Digital Test. The 6th International Workshop on Electronics, Control, Measurement and Signals, Liberec, Czechia, June 2-4, 2003, pp.266-273 (Invited plenary paper).

R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.

R.Ubar. E-Learning Tools for the Field of Electronics Design and Test. Proceedings of the 4th Int. Conf. On Information Technology Based Higher Education and Training - ITHET. Marrakech, Morocco, July 7-9, 2003, pp.285-290.

R.Ubar, E.Orasson. E-Learning tool and Exercises for Teaching Digital Test. IEEE Proceedings of 2nd Conf. on Signals, Systems, Decision and Information Technology. Sousse, Tunisia, March 26-28, 2003, CIT-6, pp.1-6.

R.Ubar, E.Rüstern, M.Kruus. EE: Eesti (Estonia) in “Towards the Harmonization of Electrical and Information Engineering Education in Europe”, Lisboa-Nancy 2003, Ed. EAEEIE, 2003, pp.67-74.

R.Ubar, J.Raik, B.Klüver. Algorithms for hierarchical fault simulation in digital systems. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.530-535.

R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

R.Ubar. Mapping Faults in Hierarchical testing of Digital Systems. Proc. of the Int. Conf. On Computer, Communication and Control technologies – CCCT’03. Orlando, USA, July 31 – August 2, 2003, pp.14-19. (Best Paper Award)

R.Ubar. Mapping Physical Defects to Logic Level for Defect Oriented Testing. Proc. of the International Symposium on Signals, Circuits and Systems – SCS 2003, Vol. 2, Iasi, Romania, July 10-11, 2003, pp.453-456.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting. IEEE Proceedings of the 21st Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.112-116.

R. Ubar. Tutorial: Hierarchical Approaches to Test Generation and Fault Simulation. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 204.

V.Hahanov, R.Ubar. Design Technologies for System-on-Chip: Fault Simulation in Complex Digital Designs. Proc. of Avtomatizirovannyje Sistemy Upravlenija i Pribory Avtomatiki”, No 122, 2003, pp.16-35 (in Russian).

V.Hahanov, R.Ubar. First East-West Design and Test Conference. IEEE Design & Test, Nov.-Dec 2003, pp.103.

V.Hahanov, R.Ubar, S.Hyduke. Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. IEEE Proceedings of the EUROMICRO Symposion on Digital System Design - DSD’2003. Belek-Antalaya, Turkey, September 3-5, 2003, pp. 370-377.

A.Jutman, A.Sudnitsõn, R.Ubar. Web-Based Applet for Teaching Boundary Scan standard IEEE 1149.1. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.584-589 (Best Paper Award).

A.Jutman, E.Aleksejev, R.Ubar. A New Evolutionary Techniques Based Approach to Optimize Pseudorandom TPG for Logic BIST. Proc. of the 1st Int. Congress on Mechanical and Electrical Engineering and Technology. Varna, October 7-11, 2002, Part I, pp.247-252.

A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics - MIEL. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.621-624.

A.Jutman, J.Raik, R.Ubar. SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms. IEEE Proceedings of the 7th European Test Workshop, Corfu, May 26-29, 2002, pp.345-346.

A.Jutman, R.Ubar, V.Hahanov, O.Skvortsova. Practical Works for On-Line Teaching Design and Test of Digital Circuits. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. III. Dubrovnik, Croatia, September 15-18, 2002, pp.1223-1226.

A.Schneider, E.Ivask, P.Mikloš, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proceedings of the Design Automation and Test in Europe – DATE’02. Paris, March 4-8, 2002, pp. 221-226.

A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, M.Fisherova, W.Pleskacz, W.Kuzmicz. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.303-306.

A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, T.Hollstein, W.Pleskacz, W.Kuzmicz, Z.Peng. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. Proceedings of the IEEE EUROMICRO Conference, September 3-6, 2002, pp. 187-195.

A.Schneider, K.-H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proceedings of the IFIP Conference on IP Based SOC Design, Grenoble, France, October 30-31, 2002, pp.357-362.

A.Schneider, K.-H.Diener, J.Raik, R.Ubar, G.Jervan, Z.Peng, T.Hollstein, M.Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. BEC-2002, Tallinn, October 6-9, 2002, pp.287-290

G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. Proceedings of the 3rd IEEE Symposium on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp.273-279

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Independent Test Sequences. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.315-318.

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests Using Branch-and-Bound and Search State Registration. IEEE Proceedings of the 7th European Test Workshop, Corfu, May 26-29, 2002, pp.19-20.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. II. Dubrovnik, Croatia, September 15-18, 2002, pp.445-448.

R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book "Microelectronics Education", Marcombo Boixareu Ed., 2002, pp.317-320

R.Ubar. E.Orasson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.659-662.

R. Ubar, E. Orasson, T. Evartson. Java Applet for Self-Learning of Digital Test Issues. Proceedings of the 13th EAEEIE Conference, York, Great Britannia, April 8-10, 2002.

R.Ubar, J.Raik, E.Ivask, M.Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, April 2002, pp.123-136

R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics - MIEL. Nis, Yugoslavia, May 12-15 2001, Vol.2, pp.617-620.

R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. Proceedings of the IEEE Workshop on Electronic Design, Test and Applications – DELTA’02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91

R.Ubar, J.Raik, E.Ivask, M.Brik. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, September 10-13, 2002, pp.315-319. Invited paper.

R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams. IEEE Proceedings of the 20th Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.265-271.

R.Ubar. Testability Calculation for Digital Circuits with Decision Diagrams. Proceedings of the 3rd IEEE Latin-American Test Workshop – LATW’2002, Montevideo, Uruguay, February 10-13, 2002, pp.137-143.

S.Devadze, A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. Teaching Digital RT-Level Self-Test Using a Java Applet. IEEE Proceedings of the 20th Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar, H.-D.Wuttke. Java Technology Based Training System for Teaching Digital Design and Test. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.283-286.

S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar. WEB-Based Training System for Teaching Basics of RT-Level Digital Design, Test and Design for Test. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.699-704.

S.Devadze, A.Jutman, M.Kruus, A.Sudnitsõn, R.Ubar. WEB-Based Tools for Synthesis and Testing of Digital Devices. Proc. of the International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002, pp.I.91-I.96. (ISBN 954-9641-28-7).

T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.

T.Nõmmeots, J.Raik, R.Ubar. Testability Analysis for Efficient Register-Transfer Level Test Generation. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.555-558

A.Jutman, R.Ubar. Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.269-288

A.Jutman, R.Ubar. Laboratory Training for Teaching Design and Test of Digital Circuits. Proceedings of the Int. Conf. on Mixed Design of Integrated Circuits and Systems -MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp. 521-524.

E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.57-60.

H.Kruus, R.Ubar, G.Jervan, Z.Peng. Using Tabu Search Method for Optimizing the Cost of Hybrid BIST. Proceedings of the XVI Int. Conf. on Design of Circuits and Integrated Systems, Porto, Portugal, Nov. 20-23, 2001, pp.445-450.

J.Raik, A.Jutman, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.117-122.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search. Proceedings of the IEEE European Test Workshop, Stockholm, May 29 – June 1, 20001, pp. 207-210

M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, Dec. 2001, pp 2023-2040

R.Ubar, A.Jutman, Z.Peng. Timing simulation of digital circuits with BDDS. Proceedings of DATE, Munich, March 13-16, 2001, pp.460-466.

R.Ubar. Design Error Diagnosis in Scan-Path Designs. Proceedings of the 2nd IEEE Latin-American Test Workshop. Cancun, Mexico, February 11-14, 2001, pp. 162-168

R. Ubar, G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid BIST in Digital Systems. Proc. of the IEEE EUROMICRO Symposium on Digital Systems Design, Warsaw, September 4-6, 2001, pp.318-325

R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.

R.Ubar, J.Heinlaid, L.Raun. Improved Testability Calculation for Digital Circuits. Proceedings of the 19th IEEE Conference NORCHIP’2001, Stockholm, Sweden, pp.264-270.

R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems. Proceedings of the Int. Symp. on Signals, Circuits and Systems SCS’2001, Iasi, Romania, July 10-11, 2001, pp.181-184

R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proceedings of the 2nd IEEE Int. Symp. on Quality of Electronic Design, San Jose, California, March 26-28, 2001, pp.365-371.

T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.163-168.

T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. Proceedings of the Int. Conf. on Mixed Design of Integrated Circuits and Systems - MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp.131-136.

T.Hollstein, Z.Peng, R.Ubar, M.Glesner. Challenges for Future System-on-Chip Design. IN "Circuit Paradigm in the 21st Century". Proceedings of the European Conference on Circuit Theory and Design - ECCTD'01. Part III. Espoo, Finland, August 28-31, 2001, pp.173-176

W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Module Level Defect Simulation in Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.253-268.

A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.35-38.

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE Proceedings European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp. 319-320

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. PÜroceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.129-132.

G.Jervan, Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST. Proceedings of the IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Tokio, October 25-28, 2000, pp.283-291.

J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000

K.-H.Diener, G.Elst, E.Gramatova, W.Kuzmicz, Z.Peng, R.Ubar. Virtual Laboratory for Research in Dependable Miroelectronics. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.217-220

M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented ault Simulation for Digital Circuits. IEEE Proceedings ETW 2000, Cascais, Portugal, Mai 23-26, 2000, pp.69-74.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.

M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.145-148.

R.Ubar, A.Jutman. BEC: Increasing the Speed of Delay Simulation in Digital Circuits. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.31-34.

R.Ubar, A.Jutman. Design Error Localization in Digital Circuits by Stuck-at Fault Test Patterns. IEEE Proceedings of the 22nd Int. Conference on Microelectronics, Nis, Yugoslavia, May 14-17 2000, pp.723-726

R.Ubar, A.Jutman, Z.Peng. Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs. Proceedings of the IEEE Norchip conference, Turku, November 7-8, 2000, pp.254-261.

R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. IEEE Proceedings of the ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

R.Ubar, A.Morawiec, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. IEEE Proc. of Design Automation and Test in Europe. Paris, March 27-30, 2000, pp. 743.

R.Ubar, A.Morawiec, J.Raik. High-Level Decision Diagrams for Simulation Performance. Proc. of the World Multiconference on Systemics, Cybernetics and Informatics, SCI- 2000. Orlando, Florida, USA, July 23-26, 2000. Vol. IX Industrial Systems, pp.62-67.

R.Ubar, A.Morawiec, J.Raik. Vector Decision Diagrams for Simulation of Digital Systems. Proceedings of the DDECS’2000, Smolenice, April 5-7, 2000, pp. 44-51.

R.Ubar, D.Borrione. Design Error Diagnosis in Digital Circuits without Error Model. In VLSI: Systems on Chip, Kluwer Academic Publishers, 2000, pp.281-292.

R.Ubar, E.Orasson, H.-D.Wuttke. Interactive Teaching Software “Introduction To Digital Test”. Proceedings of the 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.949-954.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, 221-224.

R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. In “Microelectronics Education”, Kluwer Academic Publishers, Dordrecht/ Boston/London, 2000, pp. 107-110

R.Ubar. Hierarchical Approach to Test Generation for Digital Systems at System, Circuit and Defect levels. Proceedings of the 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.711-716.

R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems. Proceedings of the 1st IEEE Symp. on Quality of Electronic Design - ISQED, San Jose, California, March 20-22, 2000, pp. 189-195

R.Ubar, M.Brik. Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.533-538.

Artjom Kurbatov, MSc, 2005, superv. Raimund Ubar. SSBDD mudeli omaduste uurimine testi gen. aja vähendamiseks. TTÜ

Joachim Sudbrock, MSc, 2005, superv. Raimund Ubar. Defect-oriented ATPG for standard cell ASIC designs. TTÜ

Tatjana Shchenova, MSc, 2005, superv. Raimund Ubar. Energy minimization in HBIST for SOC. TTÜ

Artur Jutman, PhD, 2004, superv. Raimund Ubar. Selected issues of modeling, verification and testing of digit. Systems. TTÜ

Dmitri Zhukov, MSc, 2004, superv. Raimund Ubar, Artur Jutman. Development of an educational environment based on DEFSIM. TTÜ

Jekaterina Grüning, MSc, 2004, superv. Raimund Ubar. Õppevah. aines “Digit.süst. diagnostika”. Diagnostiline modelleerimine. TTÜ

Jelena Tünni, MSc, 2004, superv. Raimund Ubar. Õppevahend aines “Digit.süst. diagnostika”.Rikete süntees ja analüüs. TTÜ

Julia Smahtina, MSc, 2004, superv. Raimund Ubar. Hybrid Functional BIST. TTÜ

Maksim Jenihhin, MSc, 2004, superv. Raimund Ubar. Test Time Minimization for Parellel Hybrid BIST Architectures. TTÜ

Natalja Mazurova, MSc, 2004, superv. Raimund Ubar. Functional BIST with DFT. TTÜ

Vineeth Govind, MSc, 2004, superv. Raimund Ubar, Jaan Raik. RTL Test Point Insertion for Improving Testability in Sequential Circuits. TTÜ

Vladisl. Vislogubov, MSc, 2004, superv. Raimund Ubar. Webipõhise õppesüsteemi väljatöötamine aines Digitaalsüsteemide diagnostika. TTÜ

Elmet Orasson, MSc, 2003, superv. Raimund Ubar. Digitaalsüsteemide testi- ja diagnostika-alase õppetarkvara arendus. TTÜ

Helena Kruus, MSc, 2003, superv. Raimund Ubar. Iteratiivsed mittedeterministlikud optimeerimisalgoritmid. TTÜ

Marina Brik, PhD, 2002, superv. Raimund Ubar. Investigation and Development of Test Generation Methods for Control Part of Digital Systems. TTÜ

Rein Raidma, MSc, 2002, superv. Raimund Ubar, Jaan Raik. Kontrollitavuse parandamisel põhinev järjestikskeemide isetestimise meetod. TTÜ

Jaan Raik, PhD, 2001, superv. Raimund Ubar. Hierarchical Test Generation for Digital Circuits Represented by Decision Diagrams. TTÜ

Jaanus Heinlaid, MSc, 2001, superv. Raimund Ubar. Digitaalskeemide signaalijälgitavuste analüüs ja arvutamine. TTÜ

Lennart Raun, MSc, 2001, superv. Raimund Ubar. Digitaalskeemide signaalijuhitavuste analüüs ja arvutamine. TTÜ

Margit Aarna, MSc, 2001, superv. Raimund Ubar. Digitaalskeemide rikete paraleelne simuleerimine binaarsetel otsustusdiagrammidel. TTÜ

Artur Jutman, MSc, 1999, superv. Raimund Ubar. Design Error Diagnosis in Digital Circuits. TTÜ

Julia Dushina, PhD, 1999, superv. Dominique Borionne, Raimund Ubar. Verification formelle des resultats de la Synthese de Haut Niveau. Grenoble’i Fourier’ Ülikool

Eero Ivask, MSc, 1998, superv. Raimund Ubar. Genetic Algorithms in Test Pattern Generation. TTÜ

Gert Jervan, MSc, 1998, superv. Raimund Ubar. Decision Diagram Synthesis from VHDL. TTÜ

Priidu Paomets, MSc, 1998, superv. Raimund Ubar. An Open and Dynamic User Interface to the CAD system Turbo-Tester. TTÜ

Jaan Raik, MSc, 1997, superv. Raimund Ubar. Alternatiivsetel graafidel põhinev hierarhiline testide generaator. TTÜ

Viktor Zaugarov, MSc, 1994, superv. Raimund Ubar. Testide genereerimine mikroprotsessoritele. TTÜ

Ahto Buldas, MSc, 1993, superv. Raimund Ubar. Digitaalskeemide simuleerimise algebraliste meetodite analüüs. TTÜ

Helena Krupnova, MSc, 1993, superv. Raimund Ubar. Constraints Analysis in Hierarchical Test Generation for Digital Systems. TTÜ

Julia Dushina, MSc, 1993, superv. Raimund Ubar. Test Generation for Data Paths of Digital Systems. TTÜ

Marina Brik, MSc, 1993, superv. Raimund Ubar. Test Synthesis for Finite State Machines. TTÜ

Teet Evartson, cand, 1987, superv. Raimund Ubar. Issledovanije i razrabotka metodov poiska neispravnostei v tsifrovyh shemah. Küberneetika instituut

Andrus Voolaine, MSc, 1986, superv. Raimund Ubar. Issledovanije i razrabotka metodov mnogoznatshnogo modelirovanija neispravnostei tsivrovyh shem. Küberneetika instituut

Martin Pall, cand, 1986, superv. Raimund Ubar. Issledovanije i razrabotka metodov generirovanija testov dlja tsifrovyh shem. Küberneetika instituut

Mari Plakk, cand, 1984, superv. Raimund Ubar. Razrabotka i issledovanije metodov sinteza testov dlja dickretnyh ustroistv na osnove modeli alternativnyh grafov. küberneetika instituut

Peeter Kitsnik, cand, 1981, superv. Raimund Ubar. Issledovanije i razrabotka metodov analiza diagnostitsheskih testov dlja tsifrovyh shem. Küberneetika instituut

A.Jutman, J.Raik, R.Ubar. An Educational Environment for Digital Testing: Hardware, Tools, and Web-based Runtime Platform. Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.412-419

A.Jutman, R.Ubar, J.Raik. Generic Interconnect BIST for Network-on-Chip. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron, April 13-16, 2005, pp.224-227

A.Jutman, R.Ubar, J.Raik. New Built-In Self-Test Scheme for SoC Interconnect. Proceedings of the 9th World Multi-Conference on Systemics, Cybernetics and Informatics. July 10-13, 2005, Orlando, Florida, USA, vol.4, pp.19-24.

A.Jutman, V.Rosin, A.Sudnitson, R.Ubar, H.-D.Wuttke A System for Teaching Basic and Advanced Topics of IEEE 1149.1 Boundary Scan Standard. Proceedings of EAEEIE, June 2005. Best Paper Award.

A.Matrosova, A.Pleshkov, R.Ubar. Construction of the Tests of Combinational Circuit Failures by Analyzing the Orthogonal Disjunctive Normal Forms Represented by the Alternative Graphs. J. of Automation and Remote Control. Publisher: Springer Science & Business Media B.V., 66 (2), 2005, pp. 313-327.

A.Matrosova, A.Pleshkov, R.Ubar. Test Generation for Combinational Circuits by Orthogonal Disjunctive Normal Forms and SSBDDs. Avtomatika i Telemekhanika, No. 2, 2005, pp. 158–174 (in Russian).

E.Gramatova, M.Fisherova, R.Ubar, W.Pleskacz. Chapter 2. Defects, Faults and Fault Models. In “Handbook of Electronic Testing”. Czech TU Publishing House, Prague, 2005, pp. 26-98.

G.Jervan, R.Ubar, Z.Peng, P.Eles. Chapter 5. Test Generation: A Hierarchical Approach. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 63-77

G.Jervan, R.Ubar, Z.Peng, P.Eles. Chapter 7. An Approach to System Level DFT. In “System-level Test and Validation of Hardware/Software Systems” by M.Sonza Reorda, Z.Peng, M.Violante. Springer Series in Advanced Microelectronics, Vol.17, 2005, pp. 91-118

G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Technique for Hybrid BIST Test Set Generation. Proc. of IEEE Design and Diagnostics of Electronic Circuits and Systems - DDECS Workshop. Sopron, April 13-16, 2005, pp.182-185.

G.Jervan, Z.Peng, R.Ubar, T.Shchenova. A Hybrid BIST Energy Minimization Technique for SoC Testing. IEE Proceedings on Computers & Digital Techniques, 2005, pp.1-20 (accepted).

IEEE 10th European Test Symposium. Informal Digest of Papers. Editors: R.Ubar, P.Prinetto, B.Al-Hashimi, M.Renovell, P.Muhmenthaler, Ch. Landrault. Tallinn, Estonia, May 22-25, 2005, 286 p.

IEEE Proceedings of the 10th European Test Symposium. Editors: R.Ubar, P.Prinetto, M.Renovell, P.Muhmenthaler, Ch. Landrault. Tallinn, Estonia, May 22-25, 2005, 230 p.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Improved Fault Emulation for Synchronous Sequential Circuits. IEEE Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.72-78.

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. Deterministic Defect-Oriented Test Generation for Digital Circuits. IEEE Proceedings of the 6th Latin-American Test Workshop – LATW2005, March 30 – April 2, 2005, Salvador, Bahia, Brazil, pp.325-330

J.Raik, R.Ubar, J.Sudbrock, W.Kuzmicz, W.Pleskacz. DOT: New Deterministic Defect-Oriented ATPG Tool. Proc. of 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.96-101

J.Raik, R.Ubar, S.Devadze, A.Jutman. Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. Lecture Notes in Computer Science, Vol. 3463, Springer Verlag, Berlin, Heidelberg, New York 2005, pp. 332-344

J.Raik, T.Nõmmeots, R.Ubar. A New Testability Calculation Method to Guide RTL Test Generation. Journal of Electronic Testing: Theory and Applications – JETTA. Springer Science + Business Media, Inc. 21, pp.73-84, 2005

J.Sudbrock, J.Raik, R.Ubar, W.Kuzmicz, W.Pleskacz. Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. Proceedings of the 8th Euromicro conference on Digital Systems Design DSD2005. Porto, Aug.30 – Sept. 3, 2005, pp.79-82.

M.Balas, M.Fisherova, E.Gramatova, A.Jutman, Z.Kotasek, O.Novak, T.Pikula, J.Raik, J.Strnadel, R.Ubar, J.Zahradka. Testing Tools for Training and Education. Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.671-676.

M.Brik, E.Fomina, R.Ubar. A Proposal for Optimisation of Low-Powered FSM Testing. 3rd East-West Design & Test Workshop EWDTW-2005, Odessa, Sept. 15-18, 2005, pp.15-20.

O.Novak, E.Gramatova, R.Ubar. Handbook of Electronic Testing. CTU Printhouse, Prague, 2005, 400 p.

O.Novak, E.Gramatova, R.Ubar. IST Project REASON – Handbook of Testing Electronic Systems. IEEE Proceedings of the 5th European Dependable Computing Conf. – EDCC-5, Budapest, April 20-22, 2005, pp.15-18.

R.Ubar. Digitaalsüsteemide diagnostika. I. Diagnostiline modelleerimine. Tallinn, TTÜ Kirjastus, 2005, 148 lk.

R.Ubar, E.Gramatova, M.Fisherova. Chapter 3. Test Generation Techniques and Algorithms. In “Handbook of Electronic Testing”. Czech TU Publishing House, Prague, 2005, pp. 100-174.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Teaching Advanced Test Issues in Digital Electronics. Proceedings of the 6th IEEE International Conference on Information Technology Based Higher Education and Training - ITHET. July 7-9, 2005, Santo Domingo, pp. S2B-5 – S2B-10.

R.Ubar, H.-D.Wuttke. Research and Training Environment for Digital Design and Test. Proc. of the 8th IASTED Int. Conf. on Computers and Advanced Technology in Education. Oranjestadt, Aruba, August 29-31, 2005, pp.232-237.

R.Ubar, P.Prinetto, J.Raik. 10th IEEE European Test Symposion. IEEE Journal of Design & Test of Computers, Sept. - Oct., 2005.

R.Ubar, T.Shchenova, G.Jervan, Z.Peng. Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment. IEEE Proceedings of the 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.2-7.

T.Bengtsson, A.Jutman, R.Ubar, S.Kumar. A method for crosstalk fault detection in on-chip Buses. IEEE NORCHIP Conference, Oulu, Finland, Nov. 21-22, 2005.

T.Bengtsson, A.Jutman, S.Kumar, R.Ubar. Delay Testing of Asynchronous NOC Interconnects. Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems Kraków, 22-25 June 2005, pp.419-424.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar, J.Raik. Evolutionary Approach to Test Generation for Functional BIST. Informal Digest of Papers of the 10th IEEE European Test Symposium, May 22-25, 2005, Tallinn, pp.151-155

A.Jutman, A.Peder, J.Raik, M.Tombak, R.Ubar. Structurally Synthesized Binary Decision Diagrams. Proc. of the 6th International Workshop on Boolean Problems, Freiberg, Germany, Sept. 2004, pp.271-278

A.Jutman, A.Sudnitson, R.Ubar, and H.-D.Wuttke, "Asynchronous E-Leaning Resources for Hardware Design Issues", in Proc. International Conference on Computer Systems and Technologies (CompSysTech'2004), Sofia, Bulgaria, 2004, v. IV, pp. 11.1-11.6. (ISBN: 954-9641-38-4).

A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. E-Learning Environment in the Area of Digital Microelectronics. IEEE Proceedings of the 5th Int. Conf. on Information Technology Based Higher Education and Training - ITHET 2004, Istambul, Turkey, 31 May – 2 June 2004, pp.278-283

A.Jutman, E.Gramatova, T.Pikula, R.Ubar. E-Learning Tools for Teaching Self-Test of Digital Electronics. 15 EAEEIE International Conf. on Innovation in Education for Electrical and Information Engineering, Sofia, Bulgaria, May 27-29, 2004, pp. 267-272.

A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. 5th European Workshop on Microelectronics Education – EWME 2004, Lausanne, April 15-16, 2004, pp. 173-176.

A.Jutman, R.Ubar, H.-D.Wuttke. Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems. In “Microelectronics Education” Kluwer Academic Publishers, 2004, pp.253-258.

E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, H-D.Wuttke. Research Environment for Teaching Digital Test. Proceedings of the 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.468-473

E. Ivask, J. Raik, R. Ubar, A. Schneider. WEB-Based Environment: Remote Use of Digital Electronics Test Tools. In “Virtual Enterprises and Collaborative Networks”, Kluwer Academic Publishers, 2004, pp. 435-442.

G.Jervan, Z.Peng, R.Ubar, O.Korelina. An Improved Estimation Methodology for Hybrid BIST Cost Calculation. IEEE Proceedings of the 22nd Norchip Conference, Oslo, November 8-9, 2004, pp.297-300.

J.Raik, A.Krivenko, R.Ubar. Comparative Analysis of Sequential Circuit Test Generation Approaches. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.225-228.

J.Raik, E.Orasson, R.Ubar. Sequential Circuits BIST with Status BIT Control. Proceedings of the Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.507-510.

J.Raik, P.Ellervee, V.Tihhomirov, R.Ubar. Fast Fault Emulation for Synchronous Sequential Circuits. 2nd IEEE East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.35-40.

J.Raik, R.Ubar. Enhancing Hierarchical ATPG with a Functional Fault Model for Multiplexers. IEEE Proceedings of the 7th Workshop on Design and Diagnostics of Electronic Circuits and Systems – DDECS 2004. Stara Lesna, Slovakia, April 18-21, 2004, pp. 219-222.

J.Raik, R.Ubar. Targeting Conditional Operations in Sequential Test Pattern Generation. IEEE Proceedings of the 9th European Test Symposium, Ajaccio, Corsica, France, May 23-26, 2004, pp. 17-18.

J.Raik, V.Govind, R.Ubar. RT-Level Test Point Insertion for Sequential Circuits. Proc. of the IEEE 1st International Workshop on Testability Assessment – IWoTA-2004, Rennes, Nov.2, 2004, pp.34-40. IEEE Catalog Number 04EX983, ISBN 0-7803-8851-8.

M.Brik, E.Ivask, J.Raik, R.Ubar. On Using Genetic Algorithm for Test Generation. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.233-236.

M.Brik, J.Raik, R.Ubar, E.Ivask. GA-based Test Generation for Sequential Circuits. 2nd IEEE East-West Design & Test Workshop EWDTW-2004, Alushta 23-26, 2004, pp.30-34.

N.Mazurova, J.Smahtina, R.Ubar. Hybrid Functional BIST for Digital Systems. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.205-208.

P.Ellervee, J.Raik, V.Tihhomirov, R.Ubar. FPGA Based Fault Emulation of Synchronous Sequential Circuits. Proc. of the 22nd IEEE Norchip Conference, Oslo, November 8-9, 2004, pp.59-62.

R.Ubar. Diagnostic Modelling of Digital Systems with Decision Diagrams. Proceedings of Tomsk State University, No 9 (I), August 2004, pp.174-179.

R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test. Frontiers in Education Conference – FIE, Savannah, USA, October 20-23, 2004.

R.Ubar, H-D.Wuttke. Research and Training Environment for Digital Design and Test. Proceedings of the 34th ASEE/IEEE Frontiers in Education Conference, October 20-23, 2004, Savannah, GA, pp.S3F-18 to S3F-24. IEEE Catalog Number: 04CH37579. ISBN: 0-7803-8552-7. Library of Congress: 79-640910. ISSN: 0190-5848.

R.Ubar, H.-D.Wuttke. Research and Training Scenarios for Design and Test of SOC. Proc. of the World Congress on Engineering and technology Education. March 14-17, 2004, Guaruja/Santos, Brasil, pp.320-324

R.Ubar, M.Aarna, H.Kruus, J.Raik. How to Generate High Quality Tests for Digital Systems. IEEE Proceedings of the International Semiconductor Conference, CAS’2004, Sinaia, Romania, Oct. 4-6, 2004, pp.459-462.

R.Ubar, M.Aarna, M.Brik, J.Raik. High_Level Fault Modeling in Digital Systems. 49. Int. Conf. IWK, Ilmenau, Germany, September 27-30, 2004, pp.486-491.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architecture. IEEE Proceedings of the 5th Latin-American Test Workshop – LATW 2004. Cartagena, Colombia, March 8-10, 2004, pp.98-103.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. An Iterative Approach to Test Time Minimization for Parallel Hybrid BIST Architectures. System-on-Chip Conference 2004, Båstad, Sweden, April 13-14, 2004.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Hybrid BIST Optimization for Core-Based Systems with Test Pattern Broadcasting. IEEE Proceedings of the 2nd Int. Workshop on Electronic Design, Test and Applications – DELTA’04, Perth, Australia, 28-30 January 2004, pp.3-8.

R.Ubar, N.Mazurova, J.Smahtina, E.Orasson, J.Raik. HyFBIST: Hybrid Functional Built-In Self-Test in Microprogrammed Data-Paths of Digital Systems. Int. Conference MIXDES, Szczecin, June 24-26, 2004, pp.497-502.

R.Ubar, T.Vassiljeva, J.Raik, A.Jutman, M.Tombak, A.Peder. Optimization of Structurally Synthesized BDDs. Proceedings of the 4th IASTED International Conference on Modelling, Simulation and Optimization, Kauai, Hawaii, USA, August 17-19, 2004, pp.234-240.

V.Hahanov, R.Ubar. 2nd IEEE EastWest Design & Test Workshop. IEEE Journal of Design & Test of Computers, Nov.-Dec 2004, pp.594.

V.Vislogubov, A.Jutman, H.Kruus, E.Orasson, J.Raik, R.Ubar. Diagnostic Software with WEB Interface for Teaching Purposes. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.255-258.

Y.A.Skobtsov, D.E.Ivanov, V.Y.Skobtsov, R.Ubar. Evolutionary approach to the functional test generation for digital circuits. Proc. of the 9th Biennial Baltic Electronics Conference, Oct. 3-6, 2004, Tallinn, pp.229-232.

A. Jutman, A. Sudnitson, R. Ubar. Digital Design Learning System Based on Java Applets. The 4th Annual Conference of the LTSN Centre for Information and Computer Sciences, NUI Galway, Ireland, 2003, pp.183-187.

A. Jutman, A. Sudnitson, R. Ubar. Web-Based Training System for Teaching Principles of Boundary Scan Technique. EAEEIE International Conference, Lodz, Poland, 16-18 June 2003.

A.Jutman, A.Sudnitsõn, R.Ubar, D.Wuttke. Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test. Proceedings of the 4th Int. Conf. on Information Technology Based Higher Education and Training - ITHET. Marrakech, Morocco, July 7-9, 2003, pp.397-401

A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet-Based Environment MOSCITO. Proc. of 7th World Multiconference on Systemics, Cybernetics and Informatics – SCI 2003. Orlando, USA, July 27-30, 2003, pp.136-141.

G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. IEEE Proceedings of the 18th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003, pp.225-232.

G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. IEEE Proceedings of the 12th Asian Test Symposium 2003, Xi’an, China, November 17-19, 2003, pp. 318-323

J.Raik, R.Raidma, R.Ubar. Explorations in Low Area Overhead DfT Techniques for Sequential BIST. IEEE Proceedings of the 21st Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.220-223.

J.Raik, R.Ubar. DECIDER: A System for Hierarchical Test Pattern Generation. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 40-45.

J.Raik, T.Nõmmeots, R.Ubar. New Method of Testability Calculation to Guide RT-Level Test Generation. IEEE Proceedings of 4th Latin-American Test Workshop – LATW2003, Natal, Brazil, February 16-19, 2003, pp.46-51.

M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.D.Wuttke. Turbo Tester – Diagnostic Package for Research and Training. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 69-73.

R.Ubar. Decision Diagrams and Digital Test. The 6th International Workshop on Electronics, Control, Measurement and Signals, Liberec, Czechia, June 2-4, 2003, pp.266-273 (Invited plenary paper).

R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.

R.Ubar. E-Learning Tools for the Field of Electronics Design and Test. Proceedings of the 4th Int. Conf. On Information Technology Based Higher Education and Training - ITHET. Marrakech, Morocco, July 7-9, 2003, pp.285-290.

R.Ubar, E.Orasson. E-Learning tool and Exercises for Teaching Digital Test. IEEE Proceedings of 2nd Conf. on Signals, Systems, Decision and Information Technology. Sousse, Tunisia, March 26-28, 2003, CIT-6, pp.1-6.

R.Ubar, E.Rüstern, M.Kruus. EE: Eesti (Estonia) in “Towards the Harmonization of Electrical and Information Engineering Education in Europe”, Lisboa-Nancy 2003, Ed. EAEEIE, 2003, pp.67-74.

R.Ubar, J.Raik, B.Klüver. Algorithms for hierarchical fault simulation in digital systems. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.530-535.

R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In “Networks on Chip” by A.Jantsch, H.Tenhunen. Kluwer Academic Publishers, 2003, pp. 131-152.

R.Ubar. Mapping Faults in Hierarchical testing of Digital Systems. Proc. of the Int. Conf. On Computer, Communication and Control technologies – CCCT’03. Orlando, USA, July 31 – August 2, 2003, pp.14-19. (Best Paper Award)

R.Ubar. Mapping Physical Defects to Logic Level for Defect Oriented Testing. Proc. of the International Symposium on Signals, Circuits and Systems – SCS 2003, Vol. 2, Iasi, Romania, July 10-11, 2003, pp.453-456.

R.Ubar, M.Jenihhin, G.Jervan, Z.Peng. Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting. IEEE Proceedings of the 21st Conference NORCHIP’2003, Riga, Latvia, November 10-11, 2003, pp.112-116.

R. Ubar. Tutorial: Hierarchical Approaches to Test Generation and Fault Simulation. J. of Radioelectronics and Informatics, No3 (24), July – September, 2003, pp. 204.

V.Hahanov, R.Ubar. Design Technologies for System-on-Chip: Fault Simulation in Complex Digital Designs. Proc. of Avtomatizirovannyje Sistemy Upravlenija i Pribory Avtomatiki”, No 122, 2003, pp.16-35 (in Russian).

V.Hahanov, R.Ubar. First East-West Design and Test Conference. IEEE Design & Test, Nov.-Dec 2003, pp.103.

V.Hahanov, R.Ubar, S.Hyduke. Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. IEEE Proceedings of the EUROMICRO Symposion on Digital System Design - DSD’2003. Belek-Antalaya, Turkey, September 3-5, 2003, pp. 370-377.

A.Jutman, A.Sudnitsõn, R.Ubar. Web-Based Applet for Teaching Boundary Scan standard IEEE 1149.1. Proc. of the 10th Int. Conf. MIXDES 2003, Lodz, June 26-28, 2003, pp.584-589 (Best Paper Award).

A.Jutman, E.Aleksejev, R.Ubar. A New Evolutionary Techniques Based Approach to Optimize Pseudorandom TPG for Logic BIST. Proc. of the 1st Int. Congress on Mechanical and Electrical Engineering and Technology. Varna, October 7-11, 2002, Part I, pp.247-252.

A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics - MIEL. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.621-624.

A.Jutman, J.Raik, R.Ubar. SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms. IEEE Proceedings of the 7th European Test Workshop, Corfu, May 26-29, 2002, pp.345-346.

A.Jutman, R.Ubar, V.Hahanov, O.Skvortsova. Practical Works for On-Line Teaching Design and Test of Digital Circuits. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. III. Dubrovnik, Croatia, September 15-18, 2002, pp.1223-1226.

A.Schneider, E.Ivask, P.Mikloš, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proceedings of the Design Automation and Test in Europe – DATE’02. Paris, March 4-8, 2002, pp. 221-226.

A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, M.Fisherova, W.Pleskacz, W.Kuzmicz. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.303-306.

A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, T.Hollstein, W.Pleskacz, W.Kuzmicz, Z.Peng. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. Proceedings of the IEEE EUROMICRO Conference, September 3-6, 2002, pp. 187-195.

A.Schneider, K.-H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proceedings of the IFIP Conference on IP Based SOC Design, Grenoble, France, October 30-31, 2002, pp.357-362.

A.Schneider, K.-H.Diener, J.Raik, R.Ubar, G.Jervan, Z.Peng, T.Hollstein, M.Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. BEC-2002, Tallinn, October 6-9, 2002, pp.287-290

G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. Proceedings of the 3rd IEEE Symposium on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp.273-279

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Independent Test Sequences. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.315-318.

J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests Using Branch-and-Bound and Search State Registration. IEEE Proceedings of the 7th European Test Workshop, Corfu, May 26-29, 2002, pp.19-20.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. II. Dubrovnik, Croatia, September 15-18, 2002, pp.445-448.

R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book "Microelectronics Education", Marcombo Boixareu Ed., 2002, pp.317-320

R.Ubar. E.Orasson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.659-662.

R. Ubar, E. Orasson, T. Evartson. Java Applet for Self-Learning of Digital Test Issues. Proceedings of the 13th EAEEIE Conference, York, Great Britannia, April 8-10, 2002.

R.Ubar, J.Raik, E.Ivask, M.Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, April 2002, pp.123-136

R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. IEEE Proceedings of the 23rd Int. Conf. on Microelectronics - MIEL. Nis, Yugoslavia, May 12-15 2001, Vol.2, pp.617-620.

R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. Proceedings of the IEEE Workshop on Electronic Design, Test and Applications – DELTA’02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91

R.Ubar, J.Raik, E.Ivask, M.Brik. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, September 10-13, 2002, pp.315-319. Invited paper.

R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams. IEEE Proceedings of the 20th Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.265-271.

R.Ubar. Testability Calculation for Digital Circuits with Decision Diagrams. Proceedings of the 3rd IEEE Latin-American Test Workshop – LATW’2002, Montevideo, Uruguay, February 10-13, 2002, pp.137-143.

S.Devadze, A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. Teaching Digital RT-Level Self-Test Using a Java Applet. IEEE Proceedings of the 20th Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar, H.-D.Wuttke. Java Technology Based Training System for Teaching Digital Design and Test. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.283-286.

S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar. WEB-Based Training System for Teaching Basics of RT-Level Digital Design, Test and Design for Test. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.699-704.

S.Devadze, A.Jutman, M.Kruus, A.Sudnitsõn, R.Ubar. WEB-Based Tools for Synthesis and Testing of Digital Devices. Proc. of the International Conference on Computer Systems and Technologies (CompSysTech’2002), Sofia, Bulgaria, June 20-21, 2002, pp.I.91-I.96. (ISBN 954-9641-28-7).

T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.

T.Nõmmeots, J.Raik, R.Ubar. Testability Analysis for Efficient Register-Transfer Level Test Generation. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.555-558

A.Jutman, R.Ubar. Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.269-288

A.Jutman, R.Ubar. Laboratory Training for Teaching Design and Test of Digital Circuits. Proceedings of the Int. Conf. on Mixed Design of Integrated Circuits and Systems -MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp. 521-524.

E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.57-60.

H.Kruus, R.Ubar, G.Jervan, Z.Peng. Using Tabu Search Method for Optimizing the Cost of Hybrid BIST. Proceedings of the XVI Int. Conf. on Design of Circuits and Integrated Systems, Porto, Portugal, Nov. 20-23, 2001, pp.445-450.

J.Raik, A.Jutman, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.117-122.

J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search. Proceedings of the IEEE European Test Workshop, Stockholm, May 29 – June 1, 20001, pp. 207-210

M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, Dec. 2001, pp 2023-2040

R.Ubar, A.Jutman, Z.Peng. Timing simulation of digital circuits with BDDS. Proceedings of DATE, Munich, March 13-16, 2001, pp.460-466.

R.Ubar. Design Error Diagnosis in Scan-Path Designs. Proceedings of the 2nd IEEE Latin-American Test Workshop. Cancun, Mexico, February 11-14, 2001, pp. 162-168

R. Ubar, G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid BIST in Digital Systems. Proc. of the IEEE EUROMICRO Symposium on Digital Systems Design, Warsaw, September 4-6, 2001, pp.318-325

R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.

R.Ubar, J.Heinlaid, L.Raun. Improved Testability Calculation for Digital Circuits. Proceedings of the 19th IEEE Conference NORCHIP’2001, Stockholm, Sweden, pp.264-270.

R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems. Proceedings of the Int. Symp. on Signals, Circuits and Systems SCS’2001, Iasi, Romania, July 10-11, 2001, pp.181-184

R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Proceedings of the 2nd IEEE Int. Symp. on Quality of Electronic Design, San Jose, California, March 26-28, 2001, pp.365-371.

T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation. Proceedings of the Int. Conf. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.163-168.

T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. Proceedings of the Int. Conf. on Mixed Design of Integrated Circuits and Systems - MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp.131-136.

T.Hollstein, Z.Peng, R.Ubar, M.Glesner. Challenges for Future System-on-Chip Design. IN "Circuit Paradigm in the 21st Century". Proceedings of the European Conference on Circuit Theory and Design - ECCTD'01. Part III. Espoo, Finland, August 28-31, 2001, pp.173-176

W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Module Level Defect Simulation in Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.253-268.

A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.35-38.

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE Proceedings European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp. 319-320

E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. PÜroceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.129-132.

G.Jervan, Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST. Proceedings of the IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Tokio, October 25-28, 2000, pp.283-291.

J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000

K.-H.Diener, G.Elst, E.Gramatova, W.Kuzmicz, Z.Peng, R.Ubar. Virtual Laboratory for Research in Dependable Miroelectronics. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.217-220

M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented ault Simulation for Digital Circuits. IEEE Proceedings ETW 2000, Cascais, Portugal, Mai 23-26, 2000, pp.69-74.

M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.

M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.145-148.

R.Ubar, A.Jutman. BEC: Increasing the Speed of Delay Simulation in Digital Circuits. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.31-34.

R.Ubar, A.Jutman. Design Error Localization in Digital Circuits by Stuck-at Fault Test Patterns. IEEE Proceedings of the 22nd Int. Conference on Microelectronics, Nis, Yugoslavia, May 14-17 2000, pp.723-726

R.Ubar, A.Jutman, Z.Peng. Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs. Proceedings of the IEEE Norchip conference, Turku, November 7-8, 2000, pp.254-261.

R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. IEEE Proceedings of the ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

R.Ubar, A.Morawiec, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. IEEE Proc. of Design Automation and Test in Europe. Paris, March 27-30, 2000, pp. 743.

R.Ubar, A.Morawiec, J.Raik. High-Level Decision Diagrams for Simulation Performance. Proc. of the World Multiconference on Systemics, Cybernetics and Informatics, SCI- 2000. Orlando, Florida, USA, July 23-26, 2000. Vol. IX Industrial Systems, pp.62-67.

R.Ubar, A.Morawiec, J.Raik. Vector Decision Diagrams for Simulation of Digital Systems. Proceedings of the DDECS’2000, Smolenice, April 5-7, 2000, pp. 44-51.

R.Ubar, D.Borrione. Design Error Diagnosis in Digital Circuits without Error Model. In VLSI: Systems on Chip, Kluwer Academic Publishers, 2000, pp.281-292.

R.Ubar, E.Orasson, H.-D.Wuttke. Interactive Teaching Software “Introduction To Digital Test”. Proceedings of the 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.949-954.

R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. Proceedings of the 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, 221-224.

R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. In “Microelectronics Education”, Kluwer Academic Publishers, Dordrecht/ Boston/London, 2000, pp. 107-110

R.Ubar. Hierarchical Approach to Test Generation for Digital Systems at System, Circuit and Defect levels. Proceedings of the 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.711-716.

R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems. Proceedings of the 1st IEEE Symp. on Quality of Electronic Design - ISQED, San Jose, California, March 20-22, 2000, pp. 189-195

R.Ubar, M.Brik. Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.533-538.