ERIS - Eesti teadus- ja arendustegevuse infosüsteem

Elulookirjeldus (CV)
1.	Eesnimi	Märt
2.	Perekonnanimi	Saarepera
3.	Töökoht	vabakutseline
4.	Ametikoht	-
5.	Sünniaeg	10.11.1963 (päev.kuu.aasta)
6.	Haridus	1979—1982 Nõo Keskkool 1982—1989 Tallinna Tehnikaülikool 1983—1985 Nõukogude Armee 1994—1996 Tokyo Tehnoloogiainstituut, magistriõpe, MSc 1996 1996—2000 Tokyo Tehnoloogiainstituut, doktoriõpe, PhD 2000
7.	Teenistuskäik	1989—1993 Tallinna Tehnikaülikool, assistent 1992—1993 Eesti TA Küberneetika Instituut, nooremteadur 1993—1994 Tokyo Tehnoloogiainstituut, teadur 2000—2001 Tokyo Ülikool, teadur 2001—2003 Neoteny Co. Ltd., tehniline nõustaja
8.	Teaduskraad	tehnikateaduste doktor
9.	Teaduskraadi välja andnud asutus, aasta	Tokyo Tehnoloogiainstituut, 2000
10.	Tunnustused
11.	Teadusorganisatsiooniline ja –administratiivne tegevus
12.	Juhendamisel kaitstud väitekirjad
13.	Teadustöö põhisuunad	Rakenduslik infoturve ja krüptograafia, asünkroonskeemide teooria
14.	Jooksvad grandid	ETF 5870 "Riskianalüüsil põhinev turvalisuse hindamise meetod ja selle rakendused"
15.	Teaduspublikatsioonid	Ahto Buldas, Peeter Laud, Märt Saarepera, and Jan Willemson. Universally composable time-stamping schemes with audit. In ISC 2005, LNCS 3650, pp.359-373. 2005. Ahto Buldas, Märt Saarepera. On provably secure time-stamping schemes. In Advances in Cryptology -- ASIACRYPT 2004. LNCS 3329, pp.500-514. 2004. Ahto Buldas, Märt Saarepera. Electronic signature system with small number of private keys. In 2nd Annual PKI Research Workshop, pp.96—108. July, 2003. Arne Ansper, Ahto Buldas, Märt Saarepera and Jan Willemson. Improving the availability of time-stamping services. In The 6th Australasian Conference on Information Security and Privacy - ACISP'2001, Sydney, Australia, July 2-4, 2001. LNCS 2119, 360-375. Springer-Verlag, 2001. M. Saarepera, T. Yoneda, "Implementation of Quasi Delay-Insensitive Boolean Function Blocks", IEICE Trans. Inf. & Syst., Vol.E83-D No.10 pp.1879-1889 2000/10. M. Saarepera, T.Yoneda, “A Self-Timed Implementation of Boolean Functions,” In Advanced Research in Asyncronous Circuits and Systems, Barcelona, pp. 243—250, 1999. T.Yoneda, Y.Ohtsuka, M.Saarepera, “Verification of Parametrized Asyncronous Circuits: a Case Study”. Application of Concurrency to System Design, Aizu-Wakamatsu, pp. 64—74, 1998.

viimati muudetud: 13.08.2004

Curriculum Vitae (CV)
1.	First Name	Märt
2.	Surname	Saarepera
3.	Institution	independent
4.	Position	-
5.	Date of birth	10.11.1963 (day.month.year)
6.	Education	1979—1982 Nõo Secondary School 1982—1989 Tallinn Tehnical University 1983—1985 Soviet Army 1994—1996 Tokyo Institue of Technology, graduate studies, MSc 1996 1996—2000 Tokyo Institute of technology, PhD studies, PhD 2000
7.	Research and professional experience	1989—1993 Tallinn Technical University, assistant 1992—1993 Institute of Cybernetics, junior researcher 1993—1994 Tokyo Institute of Technology, researcher 2000—2001 Tokyo University, researcher
8.	Academic degree	PhD
9.	Dates and sites of earning the degrees	Tokyo Institute of Technology, 2000
10.	Honours/awards
11.	Research-administrative experience
12.	Supervised dissertations
13.	Current research program	Applied information security and cryptography, Theory of asyncronous cirquits
14.	Current grant funding	ESF 5870 "Risk analysis based method for security assessment and its applications"
15.	List of most important publications	Ahto Buldas, Peeter Laud, Märt Saarepera, and Jan Willemson. Universally composable time-stamping schemes with audit. In ISC 2005, LNCS 3650, pp.359-373. 2005. Ahto Buldas, Märt Saarepera. On provably secure time-stamping schemes. In Advances in Cryptology -- ASIACRYPT 2004. LNCS 3329, pp.500-514. 2004. Ahto Buldas, Märt Saarepera. Electronic signature system with small number of private keys. In 2nd Annual PKI Research Workshop, pp.96—108. July, 2003. Arne Ansper, Ahto Buldas, Märt Saarepera and Jan Willemson. Improving the availability of time-stamping services. In The 6th Australasian Conference on Information Security and Privacy - ACISP'2001, Sydney, Australia, July 2-4, 2001. LNCS 2119, 360-375. Springer-Verlag, 2001. M. Saarepera, T. Yoneda, "Implementation of Quasi Delay-Insensitive Boolean Function Blocks", IEICE Trans. Inf. & Syst., Vol.E83-D No.10 pp.1879-1889 2000/10. M. Saarepera, T.Yoneda, “A Self-Timed Implementation of Boolean Functions,” In Advanced Research in Asyncronous Circuits and Systems, Barcelona, pp. 243—250, 1999. T.Yoneda, Y.Ohtsuka, M.Saarepera, “Verification of Parametrized Asyncronous Circuits: a Case Study”. Application of Concurrency to System Design, Aizu-Wakamatsu, pp. 64—74, 1998.

last updated: 13.08.2004