title: Defect-Oriented Testing of Digital Circuits
reg no: ETF5649
project type: Estonian Science Foundation research grant
subject: 2.9. System Engineering and Computer Technology
status: accepted
institution: TTU Faculty of Information Technology
head of project: Raimund Ubar
duration: 01.01.2003 - 31.12.2006
description: The main goal of the current project is to develop new methods, algorithms and software tools for defect-oriented test generation and fault simulation in digital circuits.

The main problems and objectives to be investigated are:
diagnostic modeling of physical defects and mapping them to the higher levels of simulation
diagnostic modeling of a special class of physical defects which change the class of the circuit (increase the number of states in the circuit)
hierarchical defect simulation in complex digital circuits
hierarchical defect-oriented test generation for complex digital circuits

The following outcome of the new project is expected:
a new Boolean differential algebra based analytical approach for defect analysis in the components of digital circuits,
a method that allows to represent physical defects on logical and higher register transfer levels for diagnostic purposes,
a new method and algorithms for hierarchical defect-oriented fault simulation in complex circuits,
a new method and algorithms for hierarchical test generation in digital circuits,
software tools for hierarchical defect-oriented test generation and fault simulation in digital circuits,
experimental research on hierarchical defect oriented fault simulation and test generation with the goal to prove the efficiency of new methods compared to the existing available methods and tools.

project group
no name institution position  
1.Marina BrikTallinn Technical UniversityResearcher 
2.Teet EvartsonTallinn Technical UniversityAssoc. Prof. 
3.Eero IvaskTallinn Technical UniversityResearcher 
4.Priidu PaometsTallinn Technical UniversityResearcher 
5.Raimund UbarTTU Faculty of Information TechnologyProfessor, TTU