| title: | FPGA Based Environment for Design Validation |
|---|---|
| reg no: | ETF6717 |
| project type: | Estonian Science Foundation research grant |
| subject: |
2.9. System Engineering and Computer Technology |
| status: | accepted |
| institution: | TTU Faculty of Information Technology |
| head of project: | Peeter Ellervee |
| duration: | 01.01.2006 - 31.12.2009 |
| description: | Validation is usually referred to as checking the functionality of a digital system by the means of simulation. The main goal of the project is to develop an environment for simulation speedup in hardware (emulation). This is based on assumptions that a system specification, described in a hardware description language (VHDL, Verilog, SystemC), can be partitioned in a such way that styles corresponding to different abstraction levels could be modeled using different simulators/emulators. Three styles can be outlined as follows: 1) Register-transfer level that is synthesizable and therefore directly implementable on FPGA. 2) Behavioral (functional) level that is synthesizable by high-level synthesis tools under certain circumstances. It should be noted that the synthesis results may not be optimal. 3) The rest, essentially software, has lost hardware related issues from its abstraction and is therefore compilable for the used processor. This allows to use simplified simulators. The main tasks and expected results are as follows: 1) Methodology and tools to group constructions of hardware description languages on the bases of synthesizability. 2) Architectural solutions how to implement execution units (processors) – instruction set, memories, interfaces – and methods to evaluate their usefulness at different abstraction levels. 3) Simplified simulation engines that cover the constructions to be implemented (there is a smaller number of them compared against full scale simulators). 4) Interfaces and synchronization mechanisms between execution units of different types. Software to control the emulation process. 5) Instructions (scripts) how to partition the initial description, to synthesize/compile, and how to control emulation. |
| project group | ||||
|---|---|---|---|---|
| no | name | institution | position | |
| 1. | Peeter Ellervee | Tallinna Tehnikaülikooli Infotehnoloogia teaduskond | ||
| 2. | Gert Jervan | |||
| 3. | Kalle Tammemäe | |||