| description: |
Modern SoCs are based on a single broadcast medium, such as AMBA and silicon backplane buses, with additional wiring for TAM implementation. Such schemes can no longer deliver the required global bandwidth and latency for current SoCs and the on-chip interconnect will increasingly be implemented as a network-on-chip (NoC). Testing such systems shares all the problems related to testing modern nanometer SoCs, and introduces also some additional challenges. In this project we investigate possibilities for reusing the NoC functionality for test data transportation. This is done in parallel with developemnt of efficient test strategy for such architectures and in our approach we have chosen hybrid BIST as one of the most promising technologies. In this project different optimization methods, algorithms and tools for hybrid BIST and NoC architectures will be developed. In addition, different aspects related to the fault tolerance of NoC based systems will be investigated as well. |