Peeter Ellervee

[ curriculum vitae ]

is involved in projects
no reg no project title, institution, position duration
1.ETF6717FPGA Based Environment for Design Validation
(Tallinna Tehnikaülikooli Infotehnoloogia teaduskond)
2006 - 2009
2.ETF6829Test and Fault Tolerance of Network-on-Chip Based Systems
()
2006 - 2009
3.SF0142508s03Design and Test of Digital Systems
(Tallinn Technical University, dotsent)
2003 - 2007
4.ETF5601Behavioral and Functional Partitioning of Digital Systems
(TTU Faculty of Information Technology, Assoc. Professor)
2003 - 2005
5.ETF5643Decomposition of Digital Systems Based on Quality Relationship Measures
(Tallinn Technical University, Assoc. Prof.)
2003 - 2005
6.ETF5141Distributed Controllers for Coarse-Grained Reconfigurable Hardware Architectures
(Tallinn Technical University Faculty of Information Technology, Assoc.Professor)
2002 - 2002
7.ETF4876Development of Methods of Finite State Machines Decomposition and Treir Software Web-Based Implementation
(Tallinn Technical University, dots.)
2001 - 2002
8.SF0140244s98Digitaalsüsteemide projekteerimise ja diagnostika alased uuringud, väljatöötlused ja rakendused
(Tallinn Technical University, teadur)
1998 - 2002
9.ETF4294Multiparadigm System on Chip Design Environment
(Tallinn Technical University, dots.)
2000 - 2001